I have https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s1... kit with me and I am planning on enabling simple DMA over PCIe design on this kit.
i found following user guide, which i found a good match i can start with
i started following steps as mentioned in page 13 section 2.3.
(i have quartus prime pro 20.1).
At step 11; i can not "generate example design" due to an ERROR; which I can not understand; i have attached the screenshot with error.
can you help me move past this error?
To keep you updated.
I got the same error , as you mentioned in the query , kindly allow me some time to check internally about the issue .
As an observation ,for other opn, I am not finding that error.
i have started following the use guide https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-ptile-pcie-avmm.p...
I am able to follow the guide, able to generate example design and generate SOF file.
next task - I want to extended the config address space mapping for PCIe IP above 0xFFh (to use and define PCIe DVSEC capability registers), and assign some predefined values to certain addresses in “Read Only” mode.
While generating PCIe IP through IP catalog , there was no option to define extended config space or DVSEC registers. so in order to do what i want, I started reviewing RTL files; generated by PCIe IP compilation in Quartus. Many of the files appears to be encrypted (see the screenshot); and I can not read the RTL code associated with these modules. Do you know how to decrypt these RTL files? So I can read them and identify lines of code, which needs to be modified.