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Ankit_P_Intel
Employee
172 Views

Enabling Intel® Stratix® 10 H-Tile and L-Tile Avalon® Memory Mapped (AvalonMM) Hard IP for PCI Express* on S10-DX kit

HI All

I have https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s1... kit with me and I am planning on enabling simple DMA over PCIe design on this kit.

 

i found following user guide, which i found a good match i can start with

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_pcie_avmm.pdf

 

i started following steps as mentioned in page 13 section 2.3.

(i have quartus prime pro 20.1).

 

At step 11; i can not "generate example design" due to an ERROR; which I can not understand; i have attached the screenshot with error.

PCIe-gen3-16-err1.png

 

can you help me move past this error?

 

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8 Replies
Rahul_S_Intel1
Employee
78 Views

Hi ,

Kindly give me some time to look on your issue .

Rahul_S_Intel1
Employee
78 Views

Hi ,

To keep you updated.

I got the same error , as you mentioned in the query , kindly allow me some time to check internally about the issue .

As an observation ,for other opn, I am not finding that error.

Rahul_S_Intel1
Employee
78 Views

Hi ,

I am kindly requesting to use the P tile pcie IP as attached below , the other ip may not work .

 

I will publish the kdb for your reference.

Ankit_P_Intel
Employee
78 Views

i have started following the use guide https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-ptile-pcie-avmm.p...

following question

  1. On pg 16 - step 12 c - for target development kit i see option for "Intel Stratix 10 DX P-Tile ES1 FPGA Development Kit". is this kit same as https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s1...? i have this kit and when i google "Intel Stratix 10 DX P-Tile ES1 FPGA Development Kit" it couldn't find anything and only pointed s10-dx kit link as above.
  2. i went ahead following the instructions but my compilation failed with these errors. can you help me solving these errors?compile_error1.png

 

Ankit_P_Intel
Employee
78 Views

I am able to follow the guide, able to generate example design and generate SOF file.

next task - I want to extended the config address space mapping for PCIe IP above 0xFFh (to use and define PCIe DVSEC capability registers), and assign some predefined values to certain addresses in “Read Only” mode.

While generating PCIe IP through IP catalog , there was no option to define extended config space or DVSEC registers. so in order to do what i want, I started reviewing RTL files; generated by PCIe IP compilation in Quartus. Many of the files appears to be encrypted (see the screenshot); and I can not read the RTL code associated with these modules. Do you know how to decrypt these RTL files? So I can read them and identify lines of code, which needs to be modified.

 

encrypted.png

Rahul_S_Intel1
Employee
78 Views

Hi,

May I request to open an new thread for the above question , please.

Ankit_P_Intel
Employee
78 Views

You can close this thread for now; I think I have got the user guide for p time IP I was looking for doe S10 DX kit
Rahul_S_Intel1
Employee
78 Views

Glad to know

 

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