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mho12
Novice
842 Views

Error (10822): HDL error at triangular_carrier.vhd(21): couldn't implement registers for assignments on this clock edge

THERE have some error of my code

but i don't know how to slove this problem 

can anyone help me to correct my code 

thank you so much !

this is the errror message i had:

Error (10822): HDL error at triangular_carrier.vhd(21): couldn't implement registers for assignments on this clock edge

 

this is my code:

entity triangular_carrier is

architecture Behavioral of triangular_carrier is

signal x,y:INTEGER:=0;

begin

process(clk,Ts)

begin

case x is

when 0 =>if (clk'event and clk='1') then    <---- there is my error occured

if y/=(Ts/2)then carrier <=y+1; y<=y+1;

else x<=1;carrier<=y-1;y<=y-1;

end if;

end if;

when 1 =>if (clk'event and clk='1') then

if y/=0then carrier <=y-1; y<=y-1;

else x<=0;carrier <=y+1; y<=y+1;

end if ;

end if;

when others=>null;

end case;

end process;

end Behavioral;

 

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7 Replies
152 Views

Hello Mark , In the HDL , every statement /code you write it will be good to make sure what hardware it can be realized or infer too. In most of the case synthesis tool behave very similar. For example lets take the above RTL,Case statement usually realized hardware as multiplexer ,..Now question is how you can implement multiplexer with synchronous logic, which is not possible right ?. that is why tool giving a statement " Cant implement the register logic(clocked logic) on this assignment" make sense? I would modify your code as below , if(rising_edge (clk) and clk = 1 ) then Case x is when 0 => when 1 => etc... Thank you , Regards, Sree
mho12
Novice
152 Views

i revised the code as you teach me

but i have this error message below:

Error (10500): VHDL syntax error at triangular_carrier.vhd(33) near text "process"; expecting "if"

 

there is the code i revised :

 

architecture Behavioral of triangular_carrier is

signal x,y:INTEGER:=0;

begin

process(clk,Ts)

begin

if(rising_edge (clk) and clk = 1 ) then

case x is

when 0 =>

if y/=(Ts/2)then carrier <=y+1; y<=y+1;

else x<=1;carrier<=y-1;y<=y-1;

end if;

when 1 =>

if y/=0 then carrier <=y-1; y<=y-1;

else x<=0;carrier <=y+1; y<=y+1;

end if ;

when others=>null;

end case;

end process;

end Behavioral;

 

would you tell me where am i wrong

thank you so much

mho12
Novice
152 Views

or can i change the code like this

is this same meaning of my code?

 

architecture Behavioral of triangular_carrier is

signal x,y:INTEGER:=0;

begin

process(clk,Ts)

begin

 

case x is

 

when 0 =>if (clk='1') then

if y/=(Ts/2)then carrier <=y+1; y<=y+1;

else x<=1;carrier<=y-1;y<=y-1;

end if;

end if;

 

when 1 =>if (clk='1') then

if y/=0 then carrier <=y-1; y<=y-1;

else x<=0;carrier <=y+1; y<=y+1;

end if ;

end if;

when others=>null;

end case;

end process;

end Behavioral;

 

152 Views

Hello Mark,

i am not sure about above code ..it looks same to my previous one ? ..can I ask what you trying to implement ? If you give me detail info I can try to help you out ?

 

Thank you ,

 

Regards,

Sree

mho12
Novice
152 Views

 

when i foolow your steps then revise my code as you teach

it will have this error message :

Error (10500): VHDL syntax error at triangular_carrier.vhd(33) near text "process"; expecting "if"

 

And this is the code which i revised

 

architecture Behavioral of triangular_carrier is

signal x,y:INTEGER:=0;

begin

process(clk,Ts)

begin

if(rising_edge (clk) and clk = 1 ) then

case x is

when 0 =>

if y/=(Ts/2)then carrier <=y+1; y<=y+1;

else x<=1;carrier<=y-1;y<=y-1;

end if;

when 1 =>

if y/=0 then carrier <=y-1; y<=y-1;

else x<=0;carrier <=y+1; y<=y+1;

end if ;

when others=>null;

end case;

end process;

end Behavioral;

 

152 Views

Hello Mark,

Here is the modified code ,

you added the if condition for clk, but didnt add the end if .If it is not confidential ,and let me know what logic you plan to implement i cna help you out if i can ?

 

 

architecture Behavioral of triangular_carrier is

 

signal x,y:INTEGER:=0;

 

begin

 

process(clk,Ts)

 

begin

 

if(rising_edge (clk) and clk = 1 ) then

 

case x is

 

when 0 =>

 

if y/=(Ts/2)then 

carrier <=y+1; y<=y+1;

 

else 

x<=1;

carrier<=y-1;

y<=y-1;

end if;

 

when 1 =>

 

if y/=0 then 

carrier <=y-1; y<=y-1;

else 

x<=0;

carrier <=y+1; 

y<=y+1;

 

end if ;

 

when others=>null;

 

end case;

end if; -- Endif here misisng.

 

end process;

 

end Behavioral;

 

Thank you ,

 

regards,

Sree

152 Views

Hello Mark, Can you let me know any further question on this topic , if not can you kindly close the case ? Thank you, Regards, Sree
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