I got this error while instantiating an external IO PLL to two Serdes channels in LVDS for arria 10 device.
I need to provide two high speed clocks into one bank (eg Bank 3B) where i use two LVDS serdes channels which receive one high speed clock each into theirs IO PLL(internal one). But Quartus- Fitter shows the above mentioned error.
so cant we use an IO PLL (internal/external) to every serdes channels available in a bank??
Please let me know Is there any alternate ways to provide two clock sources to two LVDS serdes channels.
Thanks in advance.
I think pin out assignment is not correct , here is way to check quickly; Can you remove the pin assignment editor and see how quartus fit , Then compare with your assignment to get the idea where we missing ?
Thank you sree...!
I checked those pin assignments too..but that's not the issue..
Later we found that there will be only one IO PLL we can use in every IO Bank in the arria10 FPGA. But we needed 2 IO PLLs for driving 2 LVDS Serdes channels and so assigned like that. So the fitter showed IO PLL conflict issue.
Now we are planning to provide the same IO PLL to Both Serdes channels.