Error (14996): The Fitter failed to find a legal placement for all periphery components

[jerry_anto]

I'm using Cyclone V GX board and in that lvds_rx and mipi ports are on bank 4a, so we need at least 2 pll

( one for lvds and one for mipi signals)

The compiler is trying to place both in the same location which is available in bank 4a.

Error (11239): Location PLLLVDSOUTPUT_X0_Y1_N2 is already occupied by PLL_80M:pll_mipi_phy_i|PLL_80M_0002:pll_80m_inst|altera_pll:altera_pll_i|general[1].gpll~PLL_LVDS_OUTPUT.
Info (175013): The PLL LVDS output is constrained to the region (0, 1) to (68, 2) due to related logic
Info (175015): The I/O pad MIPI_CLK_0 is constrained to the location PIN_AE19 due to: User Location Constraints (PIN_AE19)
Info (14709): The constrained I/O pad is driven by this PLL LVDS output

Error (11239): Location PLLLVDSOUTPUT_X68_Y2_N2 is already occupied by LVDS_RX:LVDS_RX_ii|altlvds_rx:ALTLVDS_RX_component|LVDS_RX_lvds_rx:auto_generated|pll_ena~PLL_LVDS_OUTPUT.
Info (175013): The PLL LVDS output is constrained to the region (0, 1) to (68, 2) due to related logic
Info (175015): The I/O pad SWIR_CL_RX[2] is constrained to the location PIN_V13 due to: User Location Constraints (PIN_V13)
Info (14709): The constrained I/O pad is driven by this PLL LVDS output

Is there any way to place other available PLL to this particular bank manually ?!

Kindly let me know a solution for this.

[Ash_R_Intel]

Hello,

Please share your Quartus design archive (.qar) with us to reproduce the issue and suggest you the solution.

Regards

[jerry_anto]

Hello,

I'm attaching my Quartus design archive file  for you to replicate our issue.

Thanks.

[Ash_R_Intel]

Hi,

Thanks for sharing the design with us.

I ran the design and encountered fitter errors. Tool is complaining about more of pins in bank 4A than acceptable due to percentage of SSN that each pin contributes to. Recommend you follow the following article and the document referred in it:

https://www.intel.com/content/www/us/en/support/programmable/articles/000084790.html?erpm_id=9987570_ts1669713395072

Regards

[jerry_anto]

Hi,

The PLL is getting placed properly when we changed the pins but my issue is I need the pins to be at that 4A Bank.

As i mentioned earlier i need to know 

"Is there any way to place other available PLL to this particular bank manually ?"

Thanks in Advance.

[Ash_R_Intel]

Hi,

Please refer to the Cyclone V Handbook and the pinout file for the device. As per the pinout file there are 2 clock pins i.e. CLK2p/n and CLK3p/n in Bank 4A. Handbook shows the accessibility of the pins to the PLLs. As you can see below there are 2 PLLs which are available. As per your pin assignments, the two pins CLOCK_80M and SWIR_CL_SCLK already occupy these two PLLs. There is no way that any other clock pin can access these PLLs now. So, you will have to relocate the pins as per PLL availability of the bank pins.

Hope this info helps identify the issue.

Regards