Custom design using Arria 10 SOC, 10AS066KF40-
The clkout pin (PLL_3H_CLKOUT0P,PLL_3H_CLKOUT0,PLL_3H_FB0/LVDS3H_15P/DQ68
) which is also defined as LVDS in pin description, when used as LVDS differential input throws fitter error,
Error(175019): Illegal constraint of I/O pad to the location PIN_K12
How to disable default clockout feature of corresponding pin and enable it to accept LVDS differential input?
Thank you for your kind reply. Actually issue was with pin mapping. We have used ADS42LB69, its having LVDS clocks and data. By mistake we have mapped P(positive) pin of ADC data line to LVDS3H_15N means Positive pin was mapped to Negative pin of LVDS Bank 3H and vice versa. After swapping these pins in pin planner issue was resolved.