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ywang161
Novice
847 Views

Error (18108): Can't place multiple pins assigned to pin location Pin_XXX in Quartus 18.1.2 for a partial reconfig design

Hello,

 

I met this error while trying to fitter my partial reconfig design with Quartus:

Error (18108): Can't place multiple pins assigned to pin location Pin_AV25 (IOPAD_X233_Y12_N61) Info (18109): Pin DMBI_H2F(0)~pad is assigned to pin location Pin_AV25 (IOPAD_X233_Y12_N61) Info (18109): Pin ~ALTERA_AVST_DATA0~ is assigned to pin location Pin_AV25 (IOPAD_X233_Y12_N61) Error (18108): Can't place multiple pins assigned to pin location Pin_AW25 (IOPAD_X233_Y11_N61) Info (18109): Pin DMBI_H2F(1)~pad is assigned to pin location Pin_AW25 (IOPAD_X233_Y11_N61) Info (18109): Pin ~ALTERA_AVST_DATA1~ is assigned to pin location Pin_AW25 (IOPAD_X233_Y11_N61) Error (18108): Can't place multiple pins assigned to pin location Pin_BA25 (IOPAD_X233_Y10_N61) Info (18109): Pin DMBI_H2F(2)~pad is assigned to pin location Pin_BA25 (IOPAD_X233_Y10_N61) Info (18109): Pin ~ALTERA_AVST_DATA2~ is assigned to pin location Pin_BA25 (IOPAD_X233_Y10_N61) Error (18108): Can't place multiple pins assigned to pin location Pin_BB25 (IOPAD_X233_Y9_N61) Info (18109): Pin DMBI_H2F(3)~pad is assigned to pin location Pin_BB25 (IOPAD_X233_Y9_N61) Info (18109): Pin ~ALTERA_AVST_DATA3~ is assigned to pin location Pin_BB25 (IOPAD_X233_Y9_N61) Error (18108): Can't place multiple pins assigned to pin location Pin_AW26 (IOPAD_X233_Y8_N61) Info (18109): Pin DMBI_H2F(4)~pad is assigned to pin location Pin_AW26 (IOPAD_X233_Y8_N61) Info (18109): Pin ~ALTERA_AVST_DATA4~ is assigned to pin location Pin_AW26 (IOPAD_X233_Y8_N61) Error (18108): Can't place multiple pins assigned to pin location Pin_AY26 (IOPAD_X233_Y7_N61) Info (18109): Pin DMBI_H2F(5)~pad is assigned to pin location Pin_AY26 (IOPAD_X233_Y7_N61) Info (18109): Pin ~ALTERA_AVST_DATA5~ is assigned to pin location Pin_AY26 (IOPAD_X233_Y7_N61) Error (18108): Can't place multiple pins assigned to pin location Pin_AY24 (IOPAD_X233_Y6_N61) Info (18109): Pin DMBI_H2F(6)~pad is assigned to pin location Pin_AY24 (IOPAD_X233_Y6_N61) Info (18109): Pin ~ALTERA_AVST_DATA6~ is assigned to pin location Pin_AY24 (IOPAD_X233_Y6_N61) Error (18108): Can't place multiple pins assigned to pin location Pin_AW24 (IOPAD_X233_Y5_N61) Info (18109): Pin DMBI_H2F(7)~pad is assigned to pin location Pin_AW24 (IOPAD_X233_Y5_N61) Info (18109): Pin ~ALTERA_AVST_DATA7~ is assigned to pin location Pin_AW24 (IOPAD_X233_Y5_N61) Error (18108): Can't place multiple pins assigned to pin location Pin_AV24 (IOPAD_X233_Y4_N61) Info (18109): Pin DMBI_H2F(8)~pad is assigned to pin location Pin_AV24 (IOPAD_X233_Y4_N61) Info (18109): Pin ~ALTERA_AVST_DATA8~ is assigned to pin location Pin_AV24 (IOPAD_X233_Y4_N61) Error (18108): Can't place multiple pins assigned to pin location Pin_AV23 (IOPAD_X233_Y3_N61) Info (18109): Pin DMBI_H2F(9)~pad is assigned to pin location Pin_AV23 (IOPAD_X233_Y3_N61) Info (18109): Pin ~ALTERA_AVST_DATA9~ is assigned to pin location Pin_AV23 (IOPAD_X233_Y3_N61) Error (18108): Can't place multiple pins assigned to pin location Pin_BA23 (IOPAD_X233_Y2_N61) Info (18109): Pin DMBI_H2F(10)~pad is assigned to pin location Pin_BA23 (IOPAD_X233_Y2_N61) Info (18109): Pin ~ALTERA_AVST_DATA10~ is assigned to pin location Pin_BA23 (IOPAD_X233_Y2_N61) Error (18108): Can't place multiple pins assigned to pin location Pin_BA24 (IOPAD_X233_Y1_N61) Info (18109): Pin DMBI_H2F(11)~pad is assigned to pin location Pin_BA24 (IOPAD_X233_Y1_N61) Info (18109): Pin ~ALTERA_AVST_DATA11~ is assigned to pin location Pin_BA24 (IOPAD_X233_Y1_N61) Error (18108): Can't place multiple pins assigned to pin location Pin_BC25 (IOPAD_X233_Y12_N46) Info (18109): Pin DMBI_H2F(12)~pad is assigned to pin location Pin_BC25 (IOPAD_X233_Y12_N46) Info (18109): Pin ~ALTERA_AVST_DATA12~ is assigned to pin location Pin_BC25 (IOPAD_X233_Y12_N46) Error (18108): Can't place multiple pins assigned to pin location Pin_BD25 (IOPAD_X233_Y11_N46) Info (18109): Pin DMBI_H2F(13)~pad is assigned to pin location Pin_BD25 (IOPAD_X233_Y11_N46) Info (18109): Pin ~ALTERA_AVST_DATA13~ is assigned to pin location Pin_BD25 (IOPAD_X233_Y11_N46) Error (18108): Can't place multiple pins assigned to pin location Pin_BF25 (IOPAD_X233_Y10_N46) Info (18109): Pin DMBI_H2F(14)~pad is assigned to pin location Pin_BF25 (IOPAD_X233_Y10_N46) Info (18109): Pin ~ALTERA_AVST_DATA14~ is assigned to pin location Pin_BF25 (IOPAD_X233_Y10_N46) Error (18108): Can't place multiple pins assigned to pin location Pin_BG25 (IOPAD_X233_Y9_N46) Info (18109): Pin DMBI_H2F(15)~pad is assigned to pin location Pin_BG25 (IOPAD_X233_Y9_N46) Info (18109): Pin ~ALTERA_AVST_DATA15~ is assigned to pin location Pin_BG25 (IOPAD_X233_Y9_N46)

 

DMBI_H2F is a port in my design, which uses pin AV25, AW25, ... etc .

 

The original design without partial reconfig settings and using the same pin assignments worked well. The original design contains the same rtl code (including a stratix 10 partial reconfig controller IP using Avalon MM interface) and uses same constraints. The only difference is I added these PR settings in my tcl script :

set_instance_assignment -name PARTITION pr_partition -to counter_0 set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to counter_0 set_instance_assignment -name PLACE_REGION "X19 Y3 X38 Y22" -to counter_0 set_instance_assignment -name ROUTE_REGION "X18 Y2 X39 Y23" -to counter_0 set_instance_assignment -name RESERVE_PLACE_REGION ON -to counter_0 set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to counter_0 set_global_assignment -name REVISION_TYPE PR_BASE set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_FINAL blinking_led_static.qdb -to | -entity top set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"  

 

The FPGA I use is stratix10 1SG280H. Quartus version is Quartus Prime Pro Edition 18.1.2, which has been updated recently.

 

And I have checked in Quartus GUI that the AVST pins are set as "use as regular IO".

 

Also I found this info Error (18108): Can't place multiple pins assigned to pin location Pin_XXX (IOPAD_X224_Y12_N61), Info... , which declares a similar problem has been resolved in 18.0 Update1, but it seems to remain to me, although I'm not very sure if they are the same bug.

 

Did I do anything wrong or it's a problem of Quartus? Any help will be appreciated!! Thx in advance!

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14 Replies
sstrell
Moderator
62 Views

What method are you using to configure your device and get the PR data? If it's Avalon streaming, then those are the dedicated pins for device configuration and PR and cannot have additional functions on them. I'm guessing it worked OK earlier because you had not yet set up a PR partition and the pins could act as dual function (Avalon streaming initially for device configuration, then switching over to be GPIO).

ywang161
Novice
62 Views

I'm using the PR controller IP with Avalon MM in attachment (I compressed it because .ip file is not allowed as attachment, please unzip it) . And to get data from PR region I use IO ports (as there is just a simple counter in PR region).

The device is initially fully configured with AVST without PR, with the same pin assignment, and worked well . But in the newly added PR part, the device will be configured with Avalon MM interface by an internal host, and it seems there's nothing concerning Avalon Streaming anymore.

 

So I would like to set AVST dual purpose pins as regular IO after initial fully configuration. I tried to do this in GUI (Assignment->device->...) but it didn't work, and this line below in tcl script didn't change anything either. (accoding to reference manual)

set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"

 

ywang161
Novice
62 Views

I made this simple test to show clearly the problem I met. In this design it suppose to fully configure the device with AVST, and then PR with AVMM using a PR controller IP, in internal host PR mode. Several LED pins are assigned to AVST dual purpose pins, which are set as regular IO after configuration , and errors occur during fitter.

 

To use this test, please set your local Quartus directory in the fist lines of pin_test/synthesis/synth.sh and then run it to see the problem.

LVEZI
Beginner
62 Views

Hi,

Is there any way that someone from Intel accept to check about this issue?

62 Views

Hi,

 

Please allow me some time on this.

 

Thanks

62 Views

Hi,

 

I have reported this to the team. I will provide an update once I received their reply.

 

Thanks.

 

1507128045

ywang161
Novice
62 Views

OK thank you in advance!

Kay
Beginner
62 Views

Hi,

 

 

1. Does design use PR?

 

2. If so, how are partial bitstream transported to the FPGA in user mode.

 

 I could not find answers from the design.

 

Thanks

ywang161
Novice
62 Views

HI,

 

1.Yes the design uses PR. You can find this line in the tcl script:

set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to counter_0

2.Due to the problem in fitter, I'm not able to generate a partial bitstream. However it is supposed to be transported to FPGA through the PR Controller IP with Avalon MM interface.

 

LVEZI
Beginner
62 Views

Hi,

The partial bitstream is supposed to be transported using JTAG thanks to jtag2avmm module.

jtag2avmm => pr_ctrl => personna

 

The final need is to be able to perform a partial reprogramming from an internal cpu. We don't need to do it from external initerface.

 

Regards

LVEZI
Beginner
62 Views

Still no answer from Intel...

I created a very simple testcase based on blinking_led example (which I use to try root partitioning as described in UG-20135 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-block-based-desig... ).

In this testcase, there is no partial reconfiguration, only a partition for u_blinking_led instance.

  • Run it as is will lead to Quartus error message.
  • Comment out lines 27 to 37 relative to partition will remove this error message

I hope that this testcase will help Intel support team finding the source of our problem.

 

sstrell
Moderator
62 Views

I tried this in 19.1 and see the same thing.

 

However, I found this: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...

 

The article is old and doesn't specifically call out Stratix 10, but it does call out Arria 10, which uses a similar PR mechanism. My guess right now is that if you're using PR, these pins can't be dual purpose because they must be always available for the incoming PR bitstream.

 

Hopefully YY can confirm.

 

#iwork4intel

LVEZI
Beginner
62 Views

Thanks for your answer.

Nevertheless, my last small testcase don't use Partial Reprogramming. It only defines a partition.

To my mind, preventing partitioning when these pins are used is abusive.

ywang161
Novice
62 Views

Thank you for your help!

 

Yes maybe the article explains the error we met in the PR design, although we don't need these dual purpose pins for receiving PR bitstream in an internal host PR. As this article didn't precise if this pin assignment limitation is for internal host PR or external host PR, maybe it meant both kinds of PR.

 

However, in the response that we've posted yesterday, we've uploaded a root_partition_issue testcase. In this design we are trying to use root reuse design flow, without PR or any runtime reconfig, and we got the same error. This is confusing to us.

 

regards.