Error: Conflict PLL, Custom PHY IP 4 Lane GE with Quartus Prime Standard 30-Day Free Trial

[Le_vietnam]

Hi,

I make an example project with Custom PHY IP  for 4 Lane GE with Quartus Prime Standard 30-Day Free Trial.

FPGA Device: Cyclone V 5CGXF

When I run PnR, there are some error:

Error (11686): Your design contains more than two CMU PLLs in the same HSSI transceiver bank. Your design contains an illegal constraint in transceiver bank: Signal SGMII_TX_P[0](n) assigned to Pin PIN_U1; Signal SGMII_TX_P[1](n) assigned to Pin PIN_N1; Signal SGMII_TX_P[2](n) assigned to Pin PIN_J1; Signal SGMII_TX_P[3](n) assigned to Pin PIN_E1; . Change the location of the specified signals so that the transceiver bank contains only two PLLs.

Error (14566): The Fitter cannot place 4 periphery component(s) due to conflicts with existing constraints (4 Channel PLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (175001): The Fitter cannot place 1 Channel PLL, which is within Custom PHY ALT_XCVR2_GBE.

Please help me fix them.

[lixy]

Hi Le_vietnam,

May I know the full device part number you are using?

According to this error message, it seems the placement of the pins violated some design constraints.

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/ehssi_hssi_constraint_check_6pack_msg.htm

For different usage of transceiver, you need to follow specific placement guidelines. For example, you can find the guideline of PCIe in this chapter of Cyclone V Device Handbook: Volume 2: Transceivers.

https://www.intel.com/content/www/us/en/docs/programmable/683586/current/pcie-supported-configurations-and-placement.html

Best Regards,

Xiaoyan

[Le_vietnam]

Hello Xiaoyan,

I am working with the Cyclone V (5CGXFC5C6F23I7) and have updated the IO Assignment, as shown in the attached file.

I am using Custom PHY IP to generate Gigabit Ethernet Mode (GIGE) with both 4-lane and 5-lane SGMII configurations.

For 4-lane SGMII, I assigned the pins to GXB 1, 2, 3, 4.
For 5-lane SGMII, I assigned the pins to GXB 0, 1, 2, 3, 4.
However, I encountered errors during Place and Route (PnR):

With 4-lane SGMII (GXB 1, 2, 3, 4):

PnR fails with the following error (details in the attached file):
Error (14566): The Fitter cannot place 4 periphery components due to conflicts with existing constraints (4 Clock Divider(s)).
With 5-lane SGMII (GXB 0, 1, 2, 3, 4):

PnR also fails.
Please help me resolve these issues.

Best regards,
Le