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Error when executing testcases on TESTMAC for L1 Application


I compiled 5GNR software and trying to run testcases on TESTMAC appliacation for L1 Layer

The ouput of PHY console is exiting with an error messege as following:


The executing program located in /root/5G_Compilation/bin/nr5g/gnb/l1/l1app



ePreambleFormat = 0, config error!

phy_prach_init_params: ERROR ePreambleFormat [0] nL_RA [0] is not valid

Cleanup after [PID] 6554

rm: cannot remove ‘/mnt/huge/*’: No such file or directory


And one more error is


I am getting the below error as well in PHY console


5GNR Timer Mode

PHYDI-START[0]: Mode: 1, Count: 44, Period: 10, Numerology: 80

phydi_start phy_bbupool_reset: TODO

gnb_start_fpga: nTimerMode[1] gFpgaStarted[0]

probe FPGAs

init fpga fec CfgInfo failed

Error opening the dev node file 1


None FPGA found!



ICC Software version used:

 icc --version

icc (ICC) 20190206

Copyright (C) 1985-2019 Intel Corporation. All rights reserved.


dpdk version : 18.08.


I will provide if any information needed in the follow up mail.




0 Kudos
5 Replies
Hi, As I understand it, you seems to observe some issue when running a 5GNR software. To ensure we are on the same page, just would like to clarify with you on the following: 1. What is the specific FPGA device that you are using? 2. What is the Quartus version that you are using? 3. Are you using any FPGA devkit? If yes, mind share with me which devkit that you are using. 4. Sorry as I am not very clear about 5GNR software. Would you mind to further elaborate on it? Any reference to web would be helpful. 5. Mind share with me if you are using any ref design shared with by Intel? If yes, please feel free to share with me the design link as well as the contact person from Intel that you have been working with. Please let me know if there is any concern. Thank you. Best regards, Chee Pin

Thanks for the reply


At this point of time we are not using any hardware, Not using FPGA Dev-kit and Quartus.


Compiling 5GNR software on Intel Xeon High end Server and testing the L1 Application created by compiling the code.


Please refer to 603577-flexran-5gnr-ref-solution-phy-software-doc-v18-12!

Open pages.html, go to chapter 4. Compilation tools 4.1 Compilation. There are detailed compilation steps in this chapter and followed by testing.

I am attaching Zip file of this or you can go to web.


We are facing issues in testing the L1 layer after compilation.


Contact person from intel : Li, Minjun <minjun.li@intel.com>


Best Regards,







Hi Bhavani, Thanks for your update and clarification. For your information, generally this Forum is used to address specific inquiries related to Intel FPGA. I understand that you seems to have inquiries related to 5GNR reference solution. It would be great if you could further consult Minjun on this. Sorry for the inconvenience. Please let me know if there is any concern. Thank you. Best regards, Chee Pin
Hi Bhavani, Just would like to follow up with you are able to get in touch with Minjun? Please let me know if there is any concern. Thank you. Best regards, Chee Pin
Hi, As I understand it, it has been some time since I last heard from you. I would set this case to closed at this moment. Feel free to file a new case if you have any further question related to this request. Thank you for your understanding. Best regards, Chee Pin