I would like to implement an Ethernet core on DE2i-150 which provides Ethernet support via a Marvell 88E1111 Ethernet PHY chip. In order to start practicing, I just want to print the source and destination MAC addresses of the network packets via JTAG UART on my PC, but I don't know where to start simulating the design. I'm a software developer, but I've been working on Verilog for a couple of months, I've read a couple of books, I've completed online lessons but I don't know where to start.
Just to learn where should I start writing a very basic MAC IP core. I'm in no hurry, I just want to know the basics. Any books, tutorials, datasheets, suggestions are welcome
In fact, I am not fully mastering the FPGA jargon, but I think I want to write TSE MAC itself, the Finite State Machine, (Preamble, Start Frame Delimiter, Destination Address, Source Address, etc ...). The TSE MAC seems to abstract all details, please correct me if i miss anything.
In the first stage, the only thing I want to do is to print the source and destination addresses through JTAG. But I want to do this as soon as the destination address comes from FSM.