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Ethernet IP - AN647 changes for Cyclone IV GX board

Altera_Forum
Honored Contributor II
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Hi, 

I am trying to recompile the An647 reference design for Cyclone IV GX development board. 

 

I get the following error during compilation: 

Error (15660): inclk[0] port of Clock Control Block "clkctrl:clkctrl_inst|clkctrl_altclkctrl_5ke:clkctrl_altclkctrl_5ke_component|clkctrl1" is driven by pll:pll_0|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1], but must be driven by a clock pin 

 

As per the user guide for this component, PLL clocks can be used only with inclk[2] and inclk[3] whereas in this reference design , PLL clocks are connected to inclk[0] and inclk[1]. 

 

But strangely the reference design gets compiled for Aria II GX. Can anybody help me with this issue? 

 

Regards 

Sonali
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