Ethernet IP - AN647 changes for Cyclone IV GX board

FPGA, SoC, And CPLD Boards And Kits

FPGA Evaluation and Development Kits

Ethernet IP - AN647 changes for Cyclone IV GX board

1,200 Views

Hi,

I am trying to recompile the An647 reference design for Cyclone IV GX development board.

I get the following error during compilation:

Error (15660): inclk[0] port of Clock Control Block "clkctrl:clkctrl_inst|clkctrl_altclkctrl_5ke:clkctrl_altclkctrl_5ke_component|clkctrl1" is driven by pll:pll_0|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1], but must be driven by a clock pin

As per the user guide for this component, PLL clocks can be used only with inclk[2] and inclk[3] whereas in this reference design , PLL clocks are connected to inclk[0] and inclk[1].

But strangely the reference design gets compiled for Aria II GX. Can anybody help me with this issue?

Regards

Sonali

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.