Ethernet with NiosII on Cyclone III FPGA Board?

[Altera_Forum]

I would like to use the ethernet on the cyclone 3c120 fpga development board with NiosII and the Niche TCP/IP stack. Anybody has done this already or knows about a quick solution? The CD of this development kit containts only a basic nios2 reference design..  

 Thanks for help, Christian

[Altera_Forum]

You can use NEEK's web server design for your reference and port that system to 3C120 dev board. You need to take care of TSE's connections as 3C120 uses marvel's giga bit ethernet phy where as NEEK has national's fast ethernet phy.

[Altera_Forum]

--- Quote Start ---  I would like to use the ethernet on the cyclone 3c120 fpga development board with NiosII and the Niche TCP/IP stack. Anybody has done this already or knows about a quick solution? The CD of this development kit containts only a basic nios2 reference design..   Thanks for help, Christian  --- Quote End ---  Unfortunately, Altera doesn't have a reference ethernet design for this board, at least yet, but a few of us do have it working.  For the FPGA design, PHY pinouts must be defined from the schematic, the RGMII interface hooked up to the MAC, a PLL implemented to create the gtx_clk, and a bit of work done in the auto-generated TimeQuest TSE constraint file. (See this thread http://www.alteraforum.com/forum/showthread.php?t=3040)  The only soft MAC supported by the NicheStack is the Altera Triple Speed Ethernet. For the Nios software, simply enable uC/OS and the NicheStack, and select the tse_mac. The tse_mac driver assumes a very specific fpga design, using scatter-gather DMA to interface to the MAC, see chapter 6 of the Triple Speed Ethernet MegaCore user guide.

[Altera_Forum]

Hello, 

 for those who have experience with this or a similar design:   What true bandwidth can be achieved with this design on a GbE link?   Where is the bottleneck?   Regards,   Leon.

[Altera_Forum]

The bottleneck is the Nios processor. I talk about it on the nios forum (http://forum.niosforum.com/forum/index.php?showtopic=8751). The fastest rate I got on udp trafic with the cyclone III on the dev board was about 50Mbits/s using the Interniche TCP/IP stack and 160Mbits/s using direct calls to the ethernet driver.

[Altera_Forum]

You can also use the Avalon OpenCores 10/100 ethernet MAC. There is a full driver written for the InterNiche Stack that supports uCOSII and superloop modes of the stack. 

 The Avalon OpenCores MAC uses less resources than the Altera TSE MAC and there are no hard-coded device names in the driver that you need to worry about. There is a pretty good document explaining how to instantiate the MAC and get it up and running.  You can obtain the MAC and the driver from the NIOS forum: http://forum.niosforum.com/forum/index.php?showtopic=8287  The driver should work equally well for the regular OpenCores MAC should you decide to use it.  I have not used the 3C120 board but I have gotten both the OpenCores and TSE MAC running on the NEEK.  Jake

[Altera_Forum]

Good afternoon.  

I have a question about ethernet on the board of Cyclone III 3c120. Are there any examples for CIII (i can't find it anywhere) or we can use the example for CII?

[Altera_Forum]

There is no design example available and I think there will never be. You can't use the CII example because it uses a different chip. Altera really screwed up on the CIII kit, less than half the board is actually usable straight out of the box. 

I made a design a while ago on that kit with an Ethernet connection, but it had some restrictions (Gigabit only, need to modify the ipport.h file, etc...). I posted it a while ago on the Nios forum but can't find it now. I'll see if I can find it again.

[Altera_Forum]

I believe the designs for Simple Socket Server Plus, on the Nios Wiki, make use of the TSE and onboard 10/100/1000 port. 

 http://www.nioswiki.com/exampledesigns/simplesocketserverplus  Cheers,  - Brendan

[Altera_Forum]

Oh true. I'll bookmark this one!

[Altera_Forum]

Unfortunately, i couldn't create the project 20090508a_nios2_linux_3c120_125mhz.tar.gz (http://www.nioswiki.com/@api/deki/files/265/=20090508a_nios2_linux_3c120_125mhz.tar.gz) under the Quartus 9.0 SP1, maybe the problem is Win Vista. 

But I have found the example for CIII it is cycloneIII_3c120_embedded_v8.1.0_CDROM.zip about 58 Mb and you can download it from the altera.com.  i have succesfully compiled it under Sopc Builder 9.0 and Nios II IDE 9.0 SP1. So now i can't understand if there is enough the symbol file of Nios with pins to launch the example on the dev board, if anybody can tell me?

[Altera_Forum]

AFAIK the example design for the embedded kit uses the Ethernet interface from the daughter board so it won't work on the Cyclone III development kit alone. 

What error do you have when you try to open the first project? It should work.

[Altera_Forum]

The example of Tse (altera\81\kits\cycloneIII_3c120_embedded\examples\standard) is working only on Quartus II above 8.0 version. 

It works on 8.1 but failed on 8.0.  Now i try understand where can i find the pinouts(from shematic maybe)? And i have a question - if i try 100 mbps i should use 25Mhz clock on rx and tx clocks? Where about the pins ena_10 and eth_mode, how and where should i connect them?

[Altera_Forum]

If you are sure you will be at 100Mbps, you can provide a 25MHz clock and ignore the outputs ena_10 and eth_mode. But then if for one reason or the other the PHY switches to 10Mbps or 1Gbps, you won't be able to send any packet.

[Altera_Forum]

Ok. 

But i can't understand how to pin tx and rx?  from manual on cyclone III: 25 MHz (reference clock); enet_rx_clk Input U5 Cyclone III device pin B14 ENET_GTX_CLK T8 - Clock Outputs  So how can I pin the enet_rx_clk Input Clock B14 if it generates 25Mhz clock i can't understand it.

[Altera_Forum]

Connect ENET_RX_CLK to rx_clk_to_the_tse_mac 

Connect a local 25MHz clock source to both ENET_GTX_CLK (wich is an output, not an input) and tx_clk_to_the_tse_mac

[Altera_Forum]

Unfortunally there is no information about the direction of these signals in manual for CIII: 

ENET_RX_D[3..0] ENET_TX_D[3..0] ENET_TX_EN ENET_RX_DV  How or where can i find them?  I suppose that outputs are: ENET_TX_D[3..0] ENET_TX_EN  and inputs: ENET_RX_DV ENET_RX_D[3..0]  A'm I right?

[Altera_Forum]

What do you mean? They are documented on both the board reference manual and the TSE datasheet. 

You supposed right.

[Altera_Forum]

This is the example of pin description in the cyclone III manual: 

U5 pin 2 RGMII interface receive clock 1.8 V ENET_RX_CLK B14 U5 pin 95 RGMII interface receive data bus bit 0 2.5 V ENET_RX_D0 W8 U5 pin 92 RGMII interface receive data bus bit 1 2.5 V ENET_RX_D1 AA6 U5 pin 93 RGMII interface receive data bus bit 2 2.5 V ENET_RX_D2 W7  and for examplу of flash description: Signal Name Description I/O Standard FSM_A(24:0) Address bus (word aligned) 1.8-V LVCMOS out (25 bits) FSM_D(15:0) Data bus N/A (Accounted for in SRAM section) FLASH_CSn Chip select 1.8-V LVCMOS out FLASH_OEn Output enable 1.8-V LVCMOS out FLASH_WEn Write enable 1.8-V LVCMOS out FLASH_RSTn Reset 1.8-V LVCMOS out  here we can find if it is out or in.

[Altera_Forum]

receive = input 

for the flash everything is an output except the data bus that is bidirectional.

[Altera_Forum]

Hello Dai - 

Wondering if you were able to locate your Gig-E design? The design on the nioswiki has so much extra added to it (due to using the standardized linux platform w/ 2 nios devices, lcd, etc) that it is not a useful jumping off point for people who need as much free fpga space as possible...  -Chris    There is no design example available and I think there will never be. You can't use the CII example because it uses a different chip. Altera really screwed up on the CIII kit, less than half the board is actually usable straight out of the box. I made a design a while ago on that kit with an Ethernet connection, but it had some restrictions (Gigabit only, need to modify the ipport.h file, etc...). I posted it a while ago on the Nios forum but can't find it now. I'll see if I can find it again.  last edited by daixiwen : september 25th, 2009 at 01:40 am.   http://www.alteraforum.com/forum//proweb/buttons/quote.gif (http://alteraforums.net/forum/newreply.php?do=newreply&p=73089)