Please tell me the story of this part, how you discovered that it is fails part? How it was measured, and such as that. Also, did you observe a functional failure in the operation of the device?
Unfortunately, the details given is not enough to request for ERMA.
To make it easier, could you share with me ;
1. What is the failure rate? What is the failure rate vs. tested sample? Example: 2 out of 100 units.
2. What is the failure symptom? Please elaborate the failure symptom in detail.
3. When did the failure happen? How did you discover the failure?
4. How did you determine the failure? Please elaborate the procedures.
5. Does the failure unit ever working before failure?
6. Did they violate solder re-flow temperature profiles, moisture sensitivity? Please provide the re-flow temperature profiles.
7. Did you swap the failure device to a known good board? Is the failure following the device or board?
8. Is this a prototype build or volume/mass production?
9. Kindly provide quantitative investigation result that could proof the failure is Intel FPGA induced.
Please do not share confidential information publicly. If you required private message, please do let us know.
I am helping Wani as she is out for maternity leave.
Sorry but Intel still grant FA approval yet as the problem statement is not clear to us and I am not sure how you isolate the failure to Stratix IV FPGA device.
- First of all, I can only see you answered half of the questions that Zawani shared with you earlier. Can you respond to remaining questions ?
- The failure description - Timing issue had been detected on Chopin device (volatile FW). MT3T8 Chopin fixing image must not be used in FCT, as it works as screening image, to prevent misbehavior of new MT3T8 deliveries with SW Rel <= Rel 8.0.
- All these statement clearly stated your firmware design encountered timing violation due to wrong image used for production testing.
- This looks to me like your own user error from your factory site.
- May I know how do you isolate this failure to Stratix IV FPGA at all ?