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Example Projects and Board File for MAX 10 FPGA 10M50 EVAL KIT

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Dear Reader,

 

I am a Xilinx user and have used Quartus in the past.

 

Currently I am evaluating the MAX10 and may purchase the 10M50 EVAL KIT for a MIPI CSI-2 project.

 

I started with the Lite/Free Version of Quartus (17.1 and 18.1). When I create a Quartus project, I am not finding that board file. I searched the Design Store, but I didn't find the right file for the 10M50 board. I found some related files in the 10M50 ZIP file, but no clear way to use those files in a Quartus project.

 

If available, please direct me to these resources for the MAX 10 FPGA 10M50 EVAL KIT and Quartus Lite:

> Example projects

> Board file

Other getting started resources.

 

Thanks,

Dave

 

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Hi Anand,

 

Thanks for your help with this question:

> Example Projects and Board File for MAX 10 FPGA 10M50 EVAL KIT

 

I think you have given me, and directed me, to the resources that were available to you. I have purchased "eval boards" from Altera, Xilinx, Digilent, Microchip, ST Micro, and Texas Instruments.. Although eval boards often have outdated documentation, I have never seen such a lack of documentation for an eval board!

 

The plan from here is to:

> Stop work on the INTEL MAX 10 FPGA 10M50 EVAL KIT

> Buy and develop using the TERASIC DE10-LITE MAX10 EVAL BOARD

The Terasic boardo doesn't support the original MIPI CSI2 effort, but has enough resources to advance other aspects of the development.

 

Thanks,

Dave

 

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Hi Dave,

 

You can fine board file, schematic and sample golden_top project from below link download Complete kit document installation.

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-ma...

 

For more projects you can check below links

https://fpgacloud.intel.com/devstore/platform/?acds_version=any&board=37

 

Board user guide will help you to get started with board.For tools refer below links

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/tt/tt_my_first_fpga.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/tt/tt_my_first_nios_sw.pdf

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Best Regards,

Anand

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Hi Anand,

 

Thanks for the links. I have since edited the text, apparently the screens shots were deleted?

 

(a) Per the Documentation web page, I installed Quartus 15.1:

> Quartus Prime Lite (Prime and Help)

> ModelSim Starter

 

(b) Following "My first ... fpga" instructions I get these warnings:

> Not compatible with Win8 or above (I am using Win10 64bit)

> Need to download device support

Quartus 17.1 and 18.1 installed and ran with no problems.

Clicking [OK] through these appears to be dead end.

 

(c) I found these text files, they have the right information, not sure how to use them:

> golden_top.qsf

> golden_top.v

 

(d) Looking at projects I find these three. Are they "Getting Started" projects?

> MAX10 LPDDR2 ...

> MIPI CSI2

> Design Example, LPDDR2 200MHz

 

Please advise Quartus version, Getting Started projects, etc.

 

Thanks,

Dave

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​Hi,

 

  1. You can use either Quartus 17.1 and 18.1 lite, Latest version of Quartus tool is recommended.

 

Example project

1. Blinking LED with MAX 10 evaluation kit

https://www.youtube.com/watch?v=7M0BL_YD6ZE

https://www.youtube.com/watch?v=yTRiH5__A_Q

Video link shared above is for MAX 10 EVAL (10M08DA) using Quartus 14.1. Steps are same for you design just change device part number and pin assignments, Also you can use latest Quartus version.

 

2. Hello world with MAX 10 kit

Steps are same just change device part number and pin assignments also you can use latest Quartus version.

Please refer below guide

https://www.intel.com/content/www/us/en/programmable/support/training/course/oniihw.html

https://www.intel.com/content/www/us/en/programmable/support/training/course/oniisw.html

https://fpgawiki.intel.com/uploads/2/29/Hello_World_Lab_Manual.pdf(skip page 12 select empty project ->next->select device ->next->next ->finish follow rest steps and do pin assignments)

 

Regards

Anand

 

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Hi Anand,

 

I can try those steps, however when I use Quartus 18.1 it lists board files for Arrow, Altera, Terasic, and Macnica Americas, but doesn't appear to include a board for the 10M50 board. That board page says to look in the Design Store for "baseline under Design Examples:, but the Design Store has three cases for the 10M50, none are the baseline.

 

Per my original question, assuming the board file exists, where do I download and how do I install the board file? I am working in a Xilinx environment where there is a concern regarding Intel technical support. Offering a Eval Board without a board will exacerbate that Intel Support issue.

 

Thanks,

Dave

 

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Hi Dave,

 

I got your Question now.

<QUOTE>where do I download and how do I install the board file?</QUOTE>

  1. We can download .par file from link.
  2. Quartus-> files->open project ->Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus

However we have can see list of Design Templates projects (MAX10 LPDDR2, MIPI CSI2,Design Example, LPDDR2 200MHz).

 

We can have our "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits.

 

  1. From ZIP file you can find golden_top.qsf & golden_top.v files under max10-10m50-eval-board-complete-kit-document\board pin-out.
  2. Quartus->Open project->Browser to max10-10m50-eval-board-complete-kit-document\board pin-out folder -> select All files (Now we can see golden_top.v & golden_top.qsf file)-> select golden_top.qsf file ->open-> you will see New Project Wizard -> Next->you will see project name and working directory ->Next->select empty project ->Next->Next->device->device family ->max 10 ->select 10M50DAF484C6GES -> Next ->Next->finish

Now you have basic Baseline Pinout Designs.

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Regards

Anand

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Hi Anand,

 

That process worked for creating a project that incorporates the goldentop.qsf and goldentop.v files for the 10M50 board. I didn't see where that would add a "board file" for the 10M50 to Quartus, maybe that isn't relevant point for Quartus. Thanks for the explicit instructions to getting the baseline loaded.

 

From the plethora of clues from your emails and other sources, I was able to get the five LED's to blink, that VHDL is included below, including pin numbers for the clock and LEDs:

 

----------------------------------------------------------------------------

-- Adapted from https://www.youtube.com/watch?v=JJ3XkNcLdx8

-- For Intel Altera MAX 10 FPGA 10M50 EVAL KIT

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

 

entity LedFlash is

   Port

   (

      clk : in STD_LOGIC;      -- PIN_J10

      led0 : out STD_LOGIC;   -- PIN_C3

      led1 : out STD_LOGIC;   -- PIN_C4

      led2 : out STD_LOGIC;   -- PIN_C5

      led3 : out STD_LOGIC;   -- PIN_D5

      led4 : out STD_LOGIC    -- PIN_C7

   );

end LedFlash;

 

architecture Behavioral of LedFlash is

 

   signal pulse : std_LOGIC := '0';

   signal count : integer range 0 to 50000000 := 0;

 

begin

 

   counter : process(clk)

   begin

      if clk'event and clk = '1' then

         if count = 49999999 then

            count <= 0;

            pulse <= not pulse;

         else

            count <= count + 1;

         end if;

      end if;

   end process;

 

   led0 <= pulse;

   led1 <= not pulse;

   led2 <= pulse;

   led3 <= not pulse;

   led4 <= pulse;

 

end Behavioral;

----------------------------------------------------------------

 

So now I have traction, thanks,

Dave

 

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Hi Anand,

 

I have been able to reuse golden_top. qsf to port simple Xilinx VHDL test programs to Quartus. That all works fine, the pin names are converted to pin numbers, etc.

 

The next step is NIOS II. 

 

Your second link to NIOS is here and from August 2015:

> https://fpgawiki.intel.com/uploads/2/29/Hello_World_Lab_Manual.pdf(skip page 12 select empty project ->next->select device ->next->next ->finish follow rest steps and do pin assignments)

> After realizing QSYS is now PLATFORM DESIGNER

I ran into this license problem:

> Error (204012): Can't generate netlist output files because the file "... hwA/dsd/synthesis/submodules/dsd_nios2e_cpu.v" is an OpenCore Plus time-limited file.

> Remove the unlicensed cores or obtain a license for those OpenCore Plus time-limited IP cores used in the design.

> The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

 

I reworked the project with the NIOS (classic) Processor and was stuck here:

> Error: dsd.nios2_dsd: Debug slave nios2_qsys_0.jtag_debug_module not connected to instruction_master.

> I tried connection to the only link to Instruction Master, but it didn't clear the error. Later I will redo the lab from scratch.

 

Any direct documentation on how to get NIOS II running on the MAX 10 FPGA 10M50 EVAL KIT with Quartus Lite/Free would be appreciated.

 

Thanks,

Dave

 

 

 

 

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HI Dave,

 

I ran into this license problem:

 

  1. Use Quietus Lite edition
  2. In your Qsys design select Nios II core =NiosII/e

 

I reworked the project with the NIOS (classic) Processor and was stuck here:

Refer below links

https://www.youtube.com/watch?v=0k4AZmdW9Sk

https://www.youtube.com/watch?v=Z0l0GrjXn8w

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf

and check Application note AN730

 

Any direct documentation on how to get NIOS II running on the MAX 10 FPGA 10M50 EVAL KIT with Quartus Lite/Free would be appreciated.

 

We don't have direct user guide but you can use other user guides provided for max 10 for example Nios ii hello world should work fine with change in FPGA PN/device and pin assignment change with latest Quartus.

http://www.terasic.com.tw/attachment/archive/956/Max10Neek_My_First_NiosII.pdf

 

Regards

Anand

 

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Hi Anand,

 

Thanks for your help with this question:

> Example Projects and Board File for MAX 10 FPGA 10M50 EVAL KIT

 

I think you have given me, and directed me, to the resources that were available to you. I have purchased "eval boards" from Altera, Xilinx, Digilent, Microchip, ST Micro, and Texas Instruments.. Although eval boards often have outdated documentation, I have never seen such a lack of documentation for an eval board!

 

The plan from here is to:

> Stop work on the INTEL MAX 10 FPGA 10M50 EVAL KIT

> Buy and develop using the TERASIC DE10-LITE MAX10 EVAL BOARD

The Terasic boardo doesn't support the original MIPI CSI2 effort, but has enough resources to advance other aspects of the development.

 

Thanks,

Dave

 

View solution in original post

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