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Example design: Agilex I-series devkit: intel_pcie_pio_1024 not converting TLP to Avalon-MM

alexislms
New Contributor III
244 Views

Using Quartus Pro 22.1, I followed UG-20330 to generate from scratch the example design of the Agilex I-series Development Kit (ES).

 

1. Compiling, inserting the driver, the board is correctly recognized.

2. Compiling the user/example intel_fpga_pcie_link_test application

3. Running Automatic detection and 0: Link test - 100 writes and reads

 

 

*********************************************************
Intel FPGA PCIe Link Test
Version 2.0
0: Automatically select a device
1: Manually select a device
*********************************************************
> 0
Opened a handle to BAR 0 of a device with BDF 0x100

*********************************************************
 0: Link test - 100 writes and reads
 1: Write memory space
 2: Read memory space
 3: Write configuration space
 4: Read configuration space
 5: Change BAR for PIO
 6: Change device
 7: Enable SRIOV
 8: Do a link test for every enabled virtual function
    belonging to the current device
 9: Perform DMA
10: Quit program
*********************************************************

 

 I can see the TLP arriving in the FPGA but there is no Avalon-MM generated by the obscure intel_pcie_pio_1024 Intel IP core. Therefore the test fails.

 

alexislms_0-1654762946491.png

And nothing for all the 1024clocks.

 

Best regards,

0 Kudos
10 Replies
alexislms
New Contributor III
219 Views

And I am unable to simulate the design since there is an error that hasn't been answered for 1year: https://community.intel.com/t5/FPGA-Intellectual-Property/Agilex-FPGA-PCIe-Gen5-Example-Design-Simul...

('rtile_s20_v0' file missing)

 

wchiah
Employee
204 Views

Hi,


Thank you for reaching out.

Just to let you know that Intel has received your support request and I am assigned to work on it.

Allow me some time to look into your issue. I shall come back to you with the findings.


Thank you for your patience.


Best regards,

Wincent_C_Intel


wchiah
Employee
193 Views

Hi,


Thanks for sharing with me your finding.

As investigated, the error can be due to a myriad of reasons and might be difficult to pinpoint exactly.

However, I've laid out some suggestions to help us narrow this down and further confirm the root cause.



Let me know if you have any different thoughts. Hoping to hear back from you.

Regards,

Wincent_C_Intel


alexislms
New Contributor III
190 Views

@wchiah,

 

Please read again my first message.

 

1. I'm following the example design ug-20330 I mentioned, it's the same link.

2. As said, the simulation doesn't work.

 

Please confirm 1. and 2. work on your side. It isn't working for me and @TBalu (the link in my 2nd message).

 

If you don't see any issue on your side, please provide the Quartus Pro 22.1 archive project of the example design that works (hw + sim).

 

Regards,

wchiah
Employee
157 Views

Hi,

 

I do a quick check on the link in your 2nd message. 
It is running simulation in Modelsim, are you getting the same error as well if running in Modelsim ?

 

For your case, I don't see any things assign in the PIO_address. 

If you want to read/write from the FPGA via PCIe to talk to another PCIe device my suggestion is as below

  • Use the host PC to determine the PCIe address of the device you need to talk to. 
  • Configure the Qsys PCIe address remap registers so that it maps to the region of the device you want to control.
  • Issue a read/write to the Avalon-MM slave interface of the Qsys PCIe component. That Avalon-MM transaction will map to a PCIe transaction that will then perform a read/write to the PCIe device. 

Let me know if you have any other thoughts.

Regards,

Wincent_C_Intel

 

 

alexislms
New Contributor III
151 Views

Hello@wchiah,

I tried again with Questa provided with Quartus Pro 22.1 and I still see the error.

alexislms_0-1655269001132.png

In the other forum topic, @TBalu used Modelsim Intel FPGA Starter Edition 2021.1 and it didn't work.

Please provide the archive of the project whose the simulation works.

 

I see the address in the header (32'h9400_0000) and this base address is correct for the BAR0.

alexislms_1-1655269102844.png

 

I am not trying to debug the Intel's example design, I'm just reporting it isn't working when following both user guides.

The reason I tried to use the example design is to have a project that works out of the box with all the correct parameters.

Again, if it's working on your side, please provide the archive of the project.

 

Regards,

wchiah
Employee
132 Views

Hi,

 

I don’t have one I’ve personally tested for sure recently due to limited bandwidth, (will try to replicate if possible)

however, in general R-Tile is looking ok in 22.1 after referring to some internal resources.

We have a KDB that defines Known Issue focusing on 22.1, that for sure you should pay attention to:

 

Let me know if this works for you.

Regards,

Wincent_C_Intel

 

 

 


alexislms
New Contributor III
126 Views

Hi @wchiah,

 

Thank you for the links, the `rtile_s20_v0` issue doesn't appear in the KDB 22.1 pro.

I don't have a Siemens* Questa* Advanced Simulator full version therefore I'll just wait for a new version.

 

I haven't done anything more than just following the exdes user guide and it doesn't work as shown in the screenshot, I give up.

 

Thank you again for the help, please feel free to close the ticket.

Regards,

wchiah
Employee
111 Views

Hi,

 

I manage to get a set of images based on 22.1 that are proven to be working on the devkit from engineering team.
Appreciate if you try it out, let me know if the issue is still happening. I shall help to escalate this into next level

Hoping to hear back from you.
Regards,

Wincent_C_Intel

alexislms
New Contributor III
67 Views

@wchiah It doesn't work. Please provide the qar so that I can add a signaltap module.

 

alexislms_3-1656637688561.png

 

alexislms_4-1656637703948.png

 

 

 

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