External DDR2 RAM with DSP stratix III: Connections of block symbol?

[Altera_Forum]

Hey guys, 

 I am also a newbie. I am done implementing a NIOS processor with the on-chip memory. Now i want to save the Nios program code on the the chip external but on board DDR2 memory.  When I create the Block symbol with the SOPC builder. I get now a lot of outputs for the most of them I find in the reference document the suiting equivalent.  But I have some questions:  1) Why do I have for the output "mem_a_from_the_mem_if_ddr2_emif_0" a 13-port bus whereas I can find 15 adress bits in the reference document?   --- Quote Start ---  U17 pin H8 Address bit 0 DDR2_DEVA_A0 SSTL-18 class I F34 U17 pin H3 Address bit 1 DDR2_DEVA_A1 SSTL-18 class I G34 U17 pin H7 Address bit 2 DDR2_DEVA_A2 SSTL-18 class I G31 U17 pin J2 Address bit 3 DDR2_DEVA_A3 SSTL-18 class I N24 U17 pin J8 Address bit 4 DDR2_DEVA_A4 SSTL-18 class I L29 U17 pin J3 Address bit 5 DDR2_DEVA_A5 SSTL-18 class I M30 U17 pin J7 Address bit 6 DDR2_DEVA_A6 SSTL-18 class I L31 U17 pin K2 Address bit 7 DDR2_DEVA_A7 SSTL-18 class I P25 U17 pin K8 Address bit 8 DDR2_DEVA_A8 SSTL-18 class I K33 U17 pin K3 Address bit 9 DDR2_DEVA_A9 SSTL-18 class I M29 U17 pin H2 Address bit 10 DDR2_DEVA_A10 SSTL-18 class I J34 U17 pin K7 Address bit 11 DDR2_DEVA_A11 SSTL-18 class I L32 U17 pin L2 Address bit 12 DDR2_DEVA_A12 SSTL-18 class I P23 U17 pin L8 Address bit 13 DDR2_DEVA_A13 SSTL-18 class I M26 U17 pin L3 Address bit 14 DDR2_DEVA_A14 SSTL-18 class I N26  --- Quote End ---  2) What are the outputs "mem_if_ddr2_emif_0_afi_clk_out" and "mem_if_ddr2_emif_0_half_clk_out" for? And where I have to connect them?  3) What are the inputs "oct_rdn_to_the_mem_if_ddr2_emif_0" and "oct_rup_to_the_mem_if_ddr2_emif_0" for? And where I have to connect them?  4)What memory is the best to use if I have the following on my Dev. Board   --- Quote Start ---  ■ DDR2 SDRAM DIMM ■ DDR2 SDRAM device ■ QDRII SRAM ■ Synchronous SRAM (SSRAM)  --- Quote End ---   Greetings from Spain :)