If my design which use less resource of FPGA, it can run more than 500Mhz? For example, my fpga is Arria V, my design use resource less than 15%, and I only need few resource to run at more than 500Mhz, and most of design run at below 150Mhz, can this design run correctly? Because the fast clock(>500Mhz) domain is high speed lvds tx part, I have no condition to verify the result, and I only need fast clock(>500Mhz) to handle the data splits(8bit ->2bit, because serial factor is 2), can everyone have reference or opinion?
What does the data sheet say as the max clock frequency spec for the device you have?
That will give you an upper bound. Actual logic and routing delays will likely degrade that number as an actual max clock frequency.
Do I need to view the max frequency of max clock tree (globle clock and regional clock)? Or other thing? Like the below fig:
Yes, the 625/525MHz global clock max will give you an upper limit of how fast your logic can run.
Running at 80% to 90% of those limits will require careful thought on how you architect your device.
You will need (probably) lots of pipelining, and need to partition logical functions in the pipeline carefully.
Getting above 100MHz is not hard these days with a high end FPGA like the ArriaV; 200-300MHz should be achievable with some thought.
So you might think about a 2X wider pipeline running at 250MHz instead of a 1X pipeline at 500MHz. The former should be a lot easier.
Thanks, now I ensure something and I will try to do something to make my design can run correctly above 500Mhz, and verify mu design function.