FPGA logic elements cell delay

[SJeon37]

Hi,

I want to know the minimum delay time between logic elements.

With MAX 10 and CYCLONE 10 LP models, about 250 ps came out when one wire was connected from verilog.

I would like to know if there is a way to further reduce this time.

Or would you like to know if there are any products with small logic element gate delay.

Thanks for your help.

[KhaiChein_Y_Intel]

Hi,

The delay depends on the placement and routing of the logic in the design. There is no specific minimum delay value as the value varies for each of the P&R result.

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

Since there is no response from you to the previous question/reply/answer that I have provided. I shall transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Thanks

Best regards,

KhaiY