FPGA to HPS bridge on Agilex 7

[Mikhail_a]

Hello 

I'm trying to read and write from and to HPS SDRAM on Agilex 7 board

I have this configuration of fpga2hps interface:

On the other side I have two msgdma ip cores for MM to Stream and Stream to MM transfers. But MM to Stream DMA doesnt work as its busy bit is permanently set to 1. As I understood from reading the forum it can be related to fpga2sdram bridge which is not initialized right.

So my question is:

1) how to make sure my  fpga2sdram bridge is in the right condition

2) what can be wrong with the MM to Stream DMA?

DMA settings:

FPGA to HPS AXI bus state:

[Artavazd]

Sorry that was me but from another account. We can close this thread.

[EBERLAZARE_I_Intel]

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