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Facing issues with External Memory Interface IP with DDR4

mamuneeb332
Beginner
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Hello!

I am trying to connect DDR4 with my Arria 10 FPGA with the help of EMIF IP. I had gone through the example design. I had followed the complete steps from Example Guide for building the example design, also i got the waveforms in Signal Tap analyzer but those waveforms shows the Transactions between Traffic Generator and EMIF IP. I want to see the waveforms of data transfer between EMIF and DDR4. Please help me with this.
My main aim is to see the data transfer between FPGA and External Memory(DDR4) through EMIF IP.
Thanks a lot for your help.

Regards,

M A Muneeb

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sstrell
Honored Contributor III
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You can't use Signal Tap for this since those are hardened paths to the I/O.  Enable the use of the EMIF Debug Toolkit in your example design to help test and debug that part of the interface.

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mamuneeb332
Beginner
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Thank you for your reply.

Yes i tried enabling the EMIF Debug Toolkit. In the EMIF Debug toolkit also, it says all the calibration tests pass. But i am not able to find the place where i could see the required signals. Could you please help me debug with EMIF Debug Toolkit.  

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sstrell
Honored Contributor III
638 Views
Like I said there is no way to see these signals directly. You can only see them in a simulation or if you probe them external to the device.
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mamuneeb332
Beginner
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Thank you sir for your reply.
Sorry for bothering again and again.
what do you mean by seeing them in a simulation ? (Do you mean Modelsim Simulations?)
Could you please tell the steps to see the signals in simulation.

Thank you. 

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AdzimZM_Intel
Employee
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Hi,


I can see that you have mark this thread as solved. I will transition this thread to community support.

Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you.

After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you.

-Adzim


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mamuneeb332
Beginner
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Hello Sir,

I have been provided with references that allowed me to view the PNF bits in the Signal Tap Logic Analyzer. Additionally, I have obtained some data from the Efficiency Monitor using the EMIF Debug Toolkit (as shown in the attached snapshot). However, I am currently unable to determine the speed of data transfer between the FPGA and DDR4 memory, specifically the speed of reads or writes. I am seeking assistance in this matter. Please help me with this.

 

Efficiency monitor data 2.jpgThank you.

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