Failed to load ddr3 design.sof using board test system

[Altera_Forum]

Hi ,  

 I am working on a max10 development kit (with MAX1050DA fpga device on it) and I have installed fpga development software kit to configure ddr3 design (it has other design examples but i am interested in ddr3 design functionality). I have synthesized the ddr3 design and generated ddr3.sof file (ddr3 design is included in development kit software) and i could able to configure this ddr3.sof using board test system and it is reporting read/write bandwidth, Everything works perfectly until here.  My issue is when i re synthesized the ddr3 design with a simple change and trying to load the new ddr3.sof file using board test system, it reports an error shown as : failed to initialize module com.altera.bts.max10.ddr3. (Changes added to the design are really simple, just added a single signal to the existing signal tap).   I am fairly new to the altera max 10 development kit and board test system (altera software). So any help on this issue is appreciated.

[Altera_Forum]

Has any one tried changing the existing design examples in development kit software and configure the new designs? Please let me know  

 These are the existing designs in max10 development kit software  ADC BTS_CONFIG DDR3 (I am working on ddr3 design ) HDMI HSMC

[Altera_Forum]

I am also seeing the same error. I got that error when simply re-compiling the original design. The design did not meeting timing, and wasn't really even close. I am attempting to close timing without making any major changes, in the hopes that this will resolve the error. I am using 15.0.0.145. It appears that the provided design had been compiled with 15.0.0.139, which I believe had a patch related to Max10 DDR3. I assumed that the patch was included in this later version, but that may not be a valid assumption. Are you able to confirm that you were able to get a .sof that you created to work?

[Altera_Forum]

Yes i could able to work with new ddr.sof file. Can you confirm which development kit version you are using REV B or REVC .These revisions have different ddr3 pin assignments so that may be a part of the issue you are seeing. 

 These are the software revisions i am using. Quartus software : 15.0.0.145 Development kit version : REV C DDR3 design path : "altera\15.0\kits\max10_10m50daf484c6ges_fpga\examples\board_test_system\ddr3\ddr3x24\ddr3x24" (these design should be a part of your development kit software)  FYI..... I know there are few other reference designs available in altera website and i have tried working on the ddr3 design example from this source("https://cloud.altera.com/devstore/platform/15.0.0/ddr3-with-board-test-system-console/") but i couldn't able to run ddr3 test using board test system.

[Altera_Forum]

Any luck JOE?

[Altera_Forum]

This issue is fixed after exchanging few emails with altera.  

  After recompiling ddr3 design, new sof image created need to be copied over to sof folder (path to sof folder --altera\15.0\kits\max10_10m50daf484c6ges_fpga\examples\board_test_system\sof) and open BTS console and configure ddr3 design. This fixed my issue.