Hi everyone,I'd like to send data, acquired by the FPGA, to the HPS. The HPS will then send these data to a computer, using ethernet. The problem is the FPGA to HPS part needs to be really fast (around 100-150 MBytes/s). I figured out the best way to do it would be to for the FPGA to write these data in the HPS RAM, then the HPS could simply read and send them to the computer. Though, I haven't find a way yet to write in RAM from the FPGA, as the RAM is a HPS-connected peripheral. Do you have any advice ? Thanks a lots in advance.
It is relatively straightforward once you know your way around Platform Designer and can interact with Avalon-MM. Your kit should have come with a few demo apps that you can use as a starting point. Look for any apps that include terasic_hps_ddr3.qsys. Also see this thread https://www.alteraforum.com/forum/showthread.php?t=58944
Hi, and thanks for your reply.I should have mentioned it earlier, but I didn't find any design using the HPS-side RAM. Every single design I found using memory was using the on-chip memory. If I'm not wrong, on-chip memory is a virtual memory stored in the FPGA, but its main downside is its size : 65 MB, which might not be sufficient for my use case. If some of you have ideas, I'd be glad to hear some.
DE0-Nano-SoC has 1 GB of HPS-side RAM and about 3 Mb (that's megabit) of on-chip memory.It looks like the DE0-Nano-SoC package does not have any samples specifically showing how to use HPS-side RAM (which is odd, because my DE10-Nano has 3 different ones). You could grab the DE10-Nano package, take a look at e.g. the project in Demonstrations\FPGA\DDR3_RTL, and port the relevant pieces onto your board. If you want to do this without interfering with Linux on HPS, you'll probably also want to read the instructions on how to prevent Linux from using part of your RAM, in the DE10-Nano user manual section 5.6. (The rest of that section has to do with a project that demonstrates the use of Nios II, which you most definitely DON'T need.)