Fast & Large block data transfer over USB - DE1/DE2 ?

[Altera_Forum]

Hi I have a DE1 fpga module, which has a single USB port that seems to be dedicated to programming. Is it possible to use it to do fast, large block data transfers over the USB ? 

 I see quite a bit of discussion here in a similar vein, but do not see anything conclusive.  I see the USB is connected to an FTDI FT245BL - this should be capable of 1M Byte / Sec, using their D2XX Drivers. It is then connected to an Altera MAX chip.  Previous fpga modules that I have used with FTDI chips have been able to use the USB port for both programming and for data transfer.  Or am I better to junk the DE1 board and buy a DE2 which I see has a second USB port ? cheers,  Beau

[Altera_Forum]

Ah I see. I will try again tomorrow. 

cheers for that,  Beau

[Altera_Forum]

At last, progress with my Morohic II code. 

As I thought, it was configuration/set-up that needed sorting. Went back to old fpgas where things worked, realised that at the end of the program up-load I was doing various reset and config things. Now with the Morphic II, I am using their program upload .dll, but still need to do the reset and config. Will try this with the USB Blaster tomorrow.

[Altera_Forum]

But no progress with the USB Baster. 

I have added relevant bits of reset and config for the FTDI USB port, and I have tried both the bit and byte variants of the JTAG TAP machine reset.  But still get toggling on TDI Pin 9, TMS Pin 5, with TCK and TDO low.  I have confirmed that I can use the Quartus and the USB Blaster to load the Morphic II program - TCK toggles fine, showing a clock type signal, Quartus reports success, the green Init_Done light comes on, indicating programming is completed. However the program does not actually run, I assume something is holding it reset.

[Altera_Forum]

--- Quote Start ---   However the program does not actually run, I assume something is holding it reset.  --- Quote End ---    The first thing you want to do, is create a design file that you know 'does something'. My usual preference is for 'blinky LEDs'. The Morph-IC board also uses an LED on the INIT_DONE line. However, rather than generating a design file that uses INIT_DONE, I use it as a general purpose I/O, and then blink the LED. Copy the body of the attached .vhd file into an entity that describes the Morphic-II pinout, and connect the INIT_DONE as shown in this design. Then go make the pin assignments, and download with the USB-Blaster.  What does the Morphic-II use for the configuration interface from the FTDI2232? Is it using passive serial configuration like the Morph-IC, or is it using the JTAG pins? If its passive serial, then I can give you my Morph-IC programming code.  Cheers, Dave

[Altera_Forum]

Sorry, I was not clear. 

 Yes I do use a LED, but had not thought of borrowing the Init_Done LED. I just have a connector on Con_1, with a couple of LEDS. One is fed from, as you say, a 1 sec toggle driven from counters, and is a nice clear indicator that the fpga is loaded and running.  It loads and runs fine when loaded from the built-in Morphic USB connector via DS2232H pin B, using the FTDI DX call from AplX :  FTStatus ← FT_ProgramMorphICDevice Hndl FileName  I then wanted to test the USB Blaster was working, so tried loading the program that way.  I used JTAG mode - would that be correct for this method ? It appears to load (Quartus reports OK, Init_Done LED goes on), but blinky LED stays off.  Any thoughts ?

[Altera_Forum]

--- Quote Start ---   It loads and runs fine when loaded from the built-in Morphic USB connector via DS2232H pin B, using the FTDI DX call from AplX :  FTStatus ← FT_ProgramMorphICDevice Hndl FileName   --- Quote End ---  You mean 'port B'. Ok, so we know the FPGA works.    --- Quote Start ---   I then wanted to test the USB Blaster was working, so tried loading the program that way.  I used JTAG mode - would that be correct for this method ? It appears to load (Quartus reports OK, Init_Done LED goes on), but blinky LED stays off.  Any thoughts ?  --- Quote End ---  So you've got a USB-Blaster connected to the JTAG header on the Morph-IC-II board? And you know the USB-Blaster works?  Do you have the Morph-IC-II schematic? Can you probe the CONF_DONE, nSTATUS, CONFIGn, etc pins? Actually, if the FT2232 is using passive serial mode, then you can read the state of those pins via the Morph-IC-II Port B interface (since the programming interface needs to access these signals). If CONF_DONE is not high after you load the FPGA via the USB-Blaster, then it indicates a problem with the JTAG interface.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  I assume something is holding it reset.  --- Quote End ---    You can test this theory by *not* using a reset signal in your design, eg., if there is a port called ext_rstN that you are using like rstN <= ext_rstN, just change it to  rstN <= '1';  And if your design works, then you know the external reset is staying asserted.  If you look at the Morph-IC-II schematic, the reset signal is likely coming from a FT2232 GPIO, and when you load via USB-Blaster, you do not deassert that pin, so you'll need to write a program to assert/deassert the reset GPIO.  Cheers, Dave

[Altera_Forum]

Well, opening the FT2232H B port seems to start the program running : 

 (LED dim) Program the fpga via the   ,HandleB &#8592; ft_OpenSpecifiedMorphICDevice Name1 Sn1  40974824  HandleB ft_ProgramMorphICDevice File (LED toggling, INIT_DONE lit)  , Tmp_Prg &#8592; ftgetbitmode HandleB 0 0 0 1 1 1 1 0  ft_CloseMorphICDevice HandleB  (unplug USB lead from FT2232H to remove power and ensure program is wiped, re-plug) (LED dim)  (program fpga via USB Blaster - reports success) (LED off, INIT_DONE lit)  ,HandleB &#8592; ft_OpenSpecifiedMorphICDevice Name1 Sn1  40974824 (LED toggling, INIT_DONE lit)  , Tmp_UB &#8592; ftgetbitmode HandleB 0 0 0 1 1 1 1 0  So I guess the USB Blaster is working fine.

[Altera_Forum]

--- Quote Start ---  Well, opening the FT2232H B port seems to start the program running   --- Quote End ---    Are you using a reset signal in your design? Does the reset come from the FT2232? Do the bit values you show correspond to the deassertion of the reset signal - hence explaining why your configuration starts to work?  Cheers, Dave

[Altera_Forum]

Reset : 

 Yes, the design uses a reset : HW_RESET, but the connection takes some tracing :    HW_RESET, fpga pin B3 - this is labled Data3   There is an external reset :  Resetin#, connector J1-14 - this goes to the FT2232H pin 14, with a pull up resistor.  The crucial commection for the reset is from the FT2232H pin 46 : BDBUS7, again labled Data3.  I have tried setting and clearing the top bit of the FT2232H B bus, to see if I can halt the operation but not sure I am doing it right yet. Will go read the data sheet again.

[Altera_Forum]

OK I can now halt the execution by using ft_setbitmode on port B, but I do not fully know what the correct setting for all the pins should be, and can not re-start execution.

[Altera_Forum]

--- Quote Start ---   The crucial commection for the reset is from the FT2232H pin 46 : BDBUS7, again labled Data3.   --- Quote End ---  If the FT2232H is being used to configure the Cyclone using passive serial communications with a 1-bit data width, then DATA[0] is the programming signal, and DATA[7:1] are available as control signals.  If the FT2232H is being used to program the Cyclone using Fast passive parallel (FPP), then all DATA[7:0] bits are used during programming.  Once the FPGA enters user-mode, the DATA pins can be configured as user-I/O. If this is the case in the Morph-IC-II, then the 8-bit bus from the FT2232 is a user-bus once the device is configured.  Post the schematic and I'll look.  Cheers, Dave

[Altera_Forum]

OK thanks, Morphic II Schematic attached. 

 One of the thing I am not clear about, is how to use the ftdi command ft_setbitmode. It is not clear as to if 1 represents input or output, and I am not clear what I do about bi-directional lines.

[Altera_Forum]

--- Quote Start ---  Morphic II Schematic attached.   --- Quote End ---    DATA3 is just a data connection between the FT2232 and the FPGA. The FPGA can be configured to use it as a DEV_CLR signal, which is basically a reset, without actually having a reset in your top-level design entity. Personally, I'd configure the pin to be a general purpose I/O and treat it as an external reset control in the design.    --- Quote Start ---   One of the thing I am not clear about, is how to use the ftdi command ft_setbitmode.   --- Quote End ---    Set bitmode is used to change between MPSSE and regular modes.  Check out the attached programmer for the Morph-IC.  Cheers, Dave

[Altera_Forum]

Thanks indeed, reading through it .... see where bit 7 is used as nReset. 

 Also just trying to use the USB Blaster to do a SignalTap analysis of my design in the Morphic II. First time I have had a USB Blaster to be able to do this. Could be very useful ....

[Altera_Forum]

--- Quote Start ---  Thanks indeed, reading through it .... see where bit 7 is used as nReset.   --- Quote End ---    Right, that is what I wanted you to understand. However, there's two ways this signal can act as reset; it can be configured as DEV_CLRn in your Quartus project setting, and it will keep your design in reset if its held low, or you can configure it as a rstN input to your top-level design, and choose to ignore it or use it.    --- Quote Start ---   Also just trying to use the USB Blaster to do a SignalTap analysis of my design in the Morphic II. First time I have had a USB Blaster to be able to do this. Could be very useful ....  --- Quote End ---    SignalTapII is extremely useful. Learn to use it. Also learn to use Modelsim.  Cheers, Dave

[Altera_Forum]

On the Morphic II the default reset seems to be a positive logic reset, I have to invert it as the logic I am importing my code from, an EZC1USB module, was a negative logic reset. 

 -- nRESET: in std_logic; -- FPGA reset, negative on-board reset, EZC1USB   HW_RESET: in std_logic; -- FPGA reset, positive on-board reset, Morphic II   begin     nRESET <= not HW_RESET;   So indeed I can ignore it if I choose - never thought of that - though I do use it extensively to reset things before they run.  How are your further thoughts on using the USB Blaster for data I/O coming on ?

[Altera_Forum]

--- Quote Start ---  On the Morphic II the default reset seems to be a positive logic reset, I have to invert it as the logic I am importing my code from, an EZC1USB module, was a negative logic reset.   --- Quote End ---  Its just a pin, so its up to you to decide what it means :)    --- Quote Start ---   So indeed I can ignore it if I choose - never thought of that - though I do use it extensively to reset things before they run.   --- Quote End ---  I just meant ignore it while debugging. Resets are generally good to use. However, you should run them through a dual-DFF synchronizer prior to use, so that the synchronized reset deasserts synchronously.    --- Quote Start ---   How are your further thoughts on using the USB Blaster for data I/O coming on ?  --- Quote End ---  I haven't had a chance to work on it. I've been working on some TimeQuest timing analysis.  Cheers, Dave

[Altera_Forum]

Large & fast USB data transfer - well I have got no further with the DE0 and DE1 interfaces, but thought you might like to see what I have been up to using the MorphicII fpga module - see these two YouTube videos : 

http://www.youtube.com/user/labtoolsinstruments I have a new transient capture/averager module just back from assembly and under test ...

[Altera_Forum]

--- Quote Start ---   thought you might like to see what I have been up to using the MorphicII fpga module - see these two YouTube videos : http://www.youtube.com/user/labtoolsinstruments   --- Quote End ---    Cool, thanks for sharing.  I watched the Morph-IC-II video, but you didn't say anything about the actual transfer rates though.  What does SignalTap II show in the FPGA fabric? Are all samples showing up over the USB bus into the FTDI FIFOs in a single-shot?  Here's a tutorial on using the USB-Blaster directly. Its slower, since it only has a serial connection to the FPGA, but it should be pretty easy to modify for use on the DE0 and DE1.  http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial  Cheers, Dave

[Altera_Forum]

Thanks re tutorial link, Dave, I will follow it up. 

The transfer from the FTDI chip is essentially a 60MHz byte-stream (=480 Mbit/s), clocked straight into fpga 16bit memory. Default USB transfer block size up to 64kByte (can be altered) .  Video 2 shows 5MWord data vectors being binned into a 2kWord x 16bit buffer, at full rate. cheers,   Beau