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Fast & Large block data transfer over USB - DE1/DE2 ?

Altera_Forum
Honored Contributor II
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Hi I have a DE1 fpga module, which has a single USB port that seems to be dedicated to programming. Is it possible to use it to do fast, large block data transfers over the USB ? 

 

I see quite a bit of discussion here in a similar vein, but do not see anything conclusive. 

 

I see the USB is connected to an FTDI FT245BL - this should be capable of 1M Byte / Sec, using their D2XX Drivers. It is then connected to an Altera MAX chip. 

 

Previous fpga modules that I have used with FTDI chips have been able to use the USB port for both programming and for data transfer. 

 

Or am I better to junk the DE1 board and buy a DE2 which I see has a second USB port ? 

cheers, 

Beau
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Altera_Forum
Honored Contributor II
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The transfer from the FTDI chip is essentially a 60MHz byte-stream (=480 Mbit/s), clocked straight into fpga 16bit memory. 

 

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No, its not. 

 

The FTDI FT2232H  

 

http://www.ftdichip.com/support/documents/datasheets/ics/ds_ft2232h.pdf 

 

Has two FPGA interface modes: 

 

* USB to parallel FIFO transfer data rate up to 8 Mbyte/Sec 

* Single channel synchronous FIFO mode for transfers > 25 Mbytes/Sec 

 

Since the Morph-IC-II interface uses channel 1 for programming the FPGA, that means channel 2 must be operating in FIFO mode. 

 

At best, you can achieve a sustained transfer rate to the FPGA fabric of 8MB/s. However, once you account for the clock period and setup and hold times, you might get lower than this. 

 

So my question is, "what sustained transfer rate did you manage to achieve?" 

 

Tracing with SignalTap II would answer the question. 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
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Yes I used synchronous FIFO mode in the FT223H for the data channel. A tricky data sheet to read, so much in it, so many modes :  

3.4.2 FT2232H pins used in an FT245 Style Synchronous FIFO Interface :  

ADBUS[7:0] I/O D7 to D0 bidirectional FIFO data. 

I attach a cropped SignalTapII recording, being clocked at 120MHz. 

clk_ftdi is a 60 MHz Clock driven from the FTDI chip. 

The data being sent is counting up, the remaining byte-count counting down with each byte. 

https://www.alteraforum.com/forum/attachment.php?attachmentid=5807  

 

For short bursts SignalTapII shows the data being clocked in or out at every clock, then there is a variable gap between the bursts. How much of this is USB related and how much PC being other-wise occupied, I do not know. 

https://www.alteraforum.com/forum/attachment.php?attachmentid=5808  

 

With up-transfers of 1k word x 16 bit data (being scaled and then converted from 64bit floating-point data in an Apl interpreter), followed by a command to read the same block back, convert it to 64-bit floating point, error checked, and displayed on a graph, a 1.6GHz Windows 7 64bit lap-top (running a 32bit Apl interpreter) can do this continually every 50ms, with transfer delay jitter just starting to go up. Down at 20 ms the system is just not keeping up. The YouTube video was captured at 10 Hz frame rate, so I used 100ms repeat time for this.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Yes I used synchronous FIFO mode in the FT223H for the data channel. 

 

--- Quote End ---  

 

 

Nice! 

 

 

--- Quote Start ---  

 

I attach a cropped SignalTapII recording, being clocked at 120MHz. 

clk_ftdi is a 60 MHz Clock driven from the FTDI chip ... For short bursts SignalTapII shows the data being clocked in or out at every clock, then there is a variable gap between the bursts. 

 

--- Quote End ---  

 

 

Very cool! Thanks for uploading the images. 

 

The FT2232H definitely looks like the way to go for implementing a USB interface to the FPGA. I'll have to test my FT2232H mini modules :) 

 

While you were doing these tests, did you have any conflicts with the FTDI drivers and the USB-Blaster? I've seen cases where I cannot open a COM port while I have SystemConsole with a JTAG connection open. I suspect an issue with the drivers not playing nicely (since the USB-Blaster also uses FTDI drivers). 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Nice! 

.... 

While you were doing these tests, did you have any conflicts with the FTDI drivers and the USB-Blaster? .... 

Cheers, 

Dave 

--- Quote End ---  

 

 

No, none at all. Only problem I had was, when uploading the program via the USB-Blaster, it left the system still reset by the FTDI interface. SO also had to also upload at least once by the FTDI interface. The fix should be simple, but I ran out of time then.
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Altera_Forum
Honored Contributor II
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No, none at all. 

 

--- Quote End ---  

Ok, good. That just means I have a problem with my test machine. I can probably fix it by uninstalling all FTDI and Altera drivers, and then starting from scratch. 

 

 

--- Quote Start ---  

 

Only problem I had was, when uploading the program via the USB-Blaster, it left the system still reset by the FTDI interface. SO also had to also upload at least once by the FTDI interface. The fix should be simple, but I ran out of time then. 

--- Quote End ---  

On the Morph-IC, the reset signal for the FPGA was one of the FTDI outputs configured as a GPIO. You can use the ftd2xx DLL to setup the GPIOs, and then deassert the reset signal. 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
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I was going to say more, then the forum access hung : 

 

 

--- Quote Start ---  

 

I've seen cases where I cannot open a COM port while I have SystemConsole with a JTAG connection open. I suspect an issue with the drivers not playing nicely (since the USB-Blaster also uses FTDI drivers). 

 

--- Quote End ---  

 

 

Ah, I am using the FTDI D2XX direct drivers, not the com port drivers. I can talk to the .dll that uses these direct from the Apl array manipulation program that I work in. 

Actually the these drivers now also handle the com interfaces as well - it is certainly worth upgrading to the latest drivers. 

I was installing a FTDI interfaced USB relay board yesterday, for high-pressure gas flow control, and noticed that having installed as com8:, when I moved it to other usb ports it remained as com8: - a considerable improvement over what used to happen with usb com ports on a PC. 

 

 

--- Quote Start ---  

 

On the Morph-IC, the reset signal for the FPGA was one of the FTDI outputs configured as a GPIO. You can use the ftd2xx DLL to setup the GPIOs, and then deassert the reset signal. 

 

--- Quote End ---  

 

Thanks, I think I had a quick try at something like this, but was not clear about the meaning of some of the GPIO instructions - I will have another try sometime. 

 

I have been thinking in the meanwhile - you have really helped me with these discussions - now I have invested some months of work and also serious money in hiring a vhdl engineer to work on the state machine for this code, so I can not make this a habit, but would you like a (personal) copy of my interface firmware for the MorphicII or the FT2232H mini modules ? I will have to do some documentation.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

 

I was installing a FTDI interfaced USB relay board yesterday, for high-pressure gas flow control, and noticed that having installed as com8:, when I moved it to other usb ports it remained as com8: - a considerable improvement over what used to happen with usb com ports on a PC. 

 

--- Quote End ---  

This occurs if the USB device has a unique serial number. I use the FTDI tool FT_PROG to re-write the serial numbers on most devices. Eg., the USB-Blasters on my two Stratix IV GX development kits were the same, so I reprogrammed them with serial numbers S4GXDK00 and S4GXDK01. You can do the same with your FTDI cables. 

 

 

--- Quote Start ---  

 

I have been thinking in the meanwhile - you have really helped me with these discussions - now I have invested some months of work and also serious money in hiring a vhdl engineer to work on the state machine for this code, so I can not make this a habit, but would you like a (personal) copy of my interface firmware for the MorphicII or the FT2232H mini modules ? I will have to do some documentation. 

--- Quote End ---  

Sure, if you don't mind me critiquing the code :) 

 

I don't have the Morph-IC-II, so don't really care about the top-level code. But I'd be interested in your FTDI interface code. 

 

Here's how I coded an FTDI asynchronous interface; 

 

1) Created a bus functional model of the FTDI interface 

2) Created an Avalon-ST interface to the FTDI device, i.e., an FTDI-to-Avalon-ST bridge. 

3) Created an Avalon-ST to Avalon-MM master component 

4) Wired them together as an FTDI-to-Avalon-MM master. 

 

Using that interface, I can open a com port and write to an address via 

 

w 0 12345678 

 

or read and receive a response 

 

r 0 

12345678 

 

I need to document that code too :) 

 

I've also implemented a UART-to-Avalon-ST bridge, which can then be connected to the Avalon-ST to Avalon-MM master, to enable RS232 command access. Again, its in need of documentation :) 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

 

(Beau: ) 

I have been thinking in the meanwhile - you have really helped me with these discussions - now I have invested some months of work and also serious money in hiring a vhdl engineer to work on the state machine for this code, so I can not make this a habit, but would you like a (personal) copy of my interface firmware for the MorphicII or the FT2232H mini modules ? I will have to do some documentation. 

 

--- Quote End ---  

 

 

--- Quote Start ---  

 

(Dave: ) 

Sure, if you don't mind me critiquing the code :) 

 

--- Quote End ---  

 

Oh I like that, helps me improve things :) 

 

 

--- Quote Start ---  

 

(Dave: ) 

Here's how I coded an FTDI asynchronous interface; 

 

1) Created a bus functional model of the FTDI interface 

2) Created an Avalon-ST interface to the FTDI device, i.e., an FTDI-to-Avalon-ST bridge. 

3) Created an Avalon-ST to Avalon-MM master component 

4) Wired them together as an FTDI-to-Avalon-MM master. 

 

Using that interface, I can open a com port and write to an address via 

 

w 0 12345678 

 

or read and receive a response 

 

r 0 

12345678 

 

I need to document that code too :) 

 

I've also implemented a UART-to-Avalon-ST bridge, which can then be connected to the Avalon-ST to Avalon-MM master, to enable RS232 command access. Again, its in need of documentation :) 

 

--- Quote End ---  

 

Cool, sounds useful. I have not experimented much with Avalon yet, but need to .... 

 

What I have done works somewhat similarly, but does not use Avalon. It is intended for interfacing to instruments : 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=5812  

 

The FTDI 2232H connects to the USB bus and interfaces to an fpga via the A-side octal register and 4 handshake lines (up to you if you use the B-side for programming, as in the MorphicII, but it does also go like the wind). 

 

The first block "USB to Addressed Bus Interface" handles the protocol below, and transfers the info to three byte-wide busses : "Bank", "Address", "Data". 

 

There can be multiple "Banks" of instruments. 

 

Each "Instrument" within the fpga has a block of up to 256 byte-wide interface registers (that can of course be be used in groups to build wide-word registers - I have used up to 128bit words), plus the streaming byte-wide data-pipe fed at full USB2 rate. The interface registers are used for instrument configuration, control, status and low-rate data transfer. 

 

So one can read or write single or multi-byte words to a particular instrument register/register group, in a similar way to your interface, just one has to also give an 8-bit "Bank" address as well as the register address - if one omits "Bank" the software defaults to the 1st bank.  

 

I use Apl for talking to the firmware - it is interactive which means rapid development but the functions run fast as you can see in the YouTube videos. It talks directly to the .dll for the FTDI D2XX direct drivers, so one has full control over the USB data transfers and configuration. But you can use this firmware with any software that can talk to the .dlls .... 

 

The "word" read/write commands are : 

BnkAddrNb ezww Data ⍝ (Data as Nb byte range integers) 

Res←HndlBnk ezrw AddressRange ⍝ (or list) (interprets Res as N byte word) 

 

 

The data-pipe is read/write and normally would go to a memory, but in my second YouTube example it feeds a peripheral with a specific block of code that is able to eat the bytes at full USB2 rate : 

BnkAddr morphic_vector_write DataVector 

DataVector ←BnkAddr morphic_vector_read N ⍝ (reads N byte vector) 

Where Addr is normally the block start address. 

 

For those reading this that have missed the earlier reference to the link of the videos of this code running : 

http://www.youtube.com/user/labtoolsinstruments
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Altera_Forum
Honored Contributor II
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Hi Dave, 

I have completed a GUI to drive the PC to FPGA VHDL code : 

https://www.alteraforum.com/forum/attachment.php?attachmentid=5865  

Also a YouTube video showing it in action : 

http://youtu.be/eqljbdtovyy (http://youtu.be/eqljbdtovyy

Even sold my first copy ! 

 

But as I say, you have given me lots of help - if you are happy to say you will use it only on a "personal, no sharing" basis, I will send you a copy with source for the VHDL and the Apl script (but Apl GUI binary). 

 

There is a binary only free down load at : 

http://www.lab-tools.com/instrumentation/download/fpga_pc_release_tf.zip (http://www.lab-tools.com/instrumentation/download/fpga_pc_release_tf.zip

 

And I expect plenty of pointers as to where I could do things better ! :) 

cheers, 

Beau
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Altera_Forum
Honored Contributor II
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Hi Beau, 

 

 

--- Quote Start ---  

 

I have completed a GUI to drive the PC to FPGA VHDL code ... 

 

--- Quote End ---  

 

 

Awesome. I'm traveling at the moment, and only have a dial-up connection (how ancient), so I'll wait until I get a real internet connection before checking it out. 

 

 

--- Quote Start ---  

 

Even sold my first copy ! 

 

--- Quote End ---  

 

 

Nice! 

 

 

--- Quote Start ---  

 

And I expect plenty of pointers as to where I could do things better ! :) 

 

--- Quote End ---  

 

 

Next week, I'll check out the code and concept and give you my review :) 

 

Ping me next week some time, if you haven't heard from me. 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
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@BeauWebber 

 

how easy would it be to include a EPCS4 configuration eeprom to the MorphicII fpga module design? would dwh@ovro.caltech.edu test .c upload problem need any amendments to work with the EPCS4 

 

im very new to this / very interested! :)
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Altera_Forum
Honored Contributor II
226 Views

 

--- Quote Start ---  

@BeauWebber 

 

how easy would it be to include a EPCS4 configuration eeprom to the MorphicII fpga module design? would dwh@ovro.caltech.edu test .c upload problem need any amendments to work with the EPCS4 ? :) 

--- Quote End ---  

 

 

Such a configuration eeprom is not really needed - the MorphicII fpga module is programmed over the same USB as transfers data, and it only takes about 100ms for the upload and program. 

 

There is an example binary GUI with binary VHDL code that programs the MorphicII and demonstrates transferring data over the USB at full USB2 rates, at : 

http://www.lab-tools.com/instrumentation/soft-firm-hard-ware/fpga_interface_to_pc/help.html 

cheers, 

Beau
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

you can transfer your data by usb but if you can also the data by using networking. 

--- Quote End ---  

 

 

Can you please explain more ? 

I am using all the expansion IO for a Terassic ADA module - I did not think the DE1 had a LAN connection ? 

cheers, 

Beau
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