Hi,
I'm currently designing a fifo interface between the HPS and the FPGA of the DE1-SoC. All the programming is done but I'm constantly getting the value 2097152 back in my HPS with the status of the fill levels 1023.
I followed the tutorial on https://hackaday.io/project/21604-fifo-interface-between-arm-and-fpga-on-de1-soc. I've added some code and screenshots with the results.
ENTITY receiver IS
PORT (
reset : IN std_logic;
clk : IN std_logic;
ready : OUT std_logic;
board : out sudoku;
hps_to_fpga_readdata : IN std_logic_vector(31 downto 0);
hps_to_fpga_read : OUT std_logic;
hps_to_fpga_out_csr_address : IN std_logic_vector(2 downto 0) := "001" ; -- fill_level
hps_to_fpga_out_csr_readdata : IN std_logic_vector(31 downto 0);
hps_to_fpga_out_csr_read : IN std_logic; -- status regs read cmd
hps_to_fpga_out_csr_writedata : IN std_logic_vector(31 downto 0);
fpga_to_hps_in_writedata : OUT std_logic_vector(31 downto 0);
fpga_to_hps_in_write : OUT std_logic; -- write command
fpga_to_hps_in_csr_address : IN std_logic_vector(2 downto 0) := "001"; -- fill_level
fpga_to_hps_in_csr_readdata : IN std_logic_vector(31 downto 0);
fpga_to_hps_in_csr_read : IN std_logic; -- status regs read cmd
fpga_to_hps_in_csr_writedata : IN std_logic_vector(31 downto 0)
);
END ENTITY receiver;
ARCHITECTURE behaviour OF receiver IS
signal data_buffer : std_logic_vector(31 downto 0);
signal data_buffer_valid : std_logic;
BEGIN
PROCESS(clk, reset)
variable state : integer := 0;
variable state2 : integer := 0;
BEGIN
if reset = '0' then
ready <= '0';
state := 0;
state2 := 0;
elsif rising_edge(clk) then
if (state = 0 and not(hps_to_fpga_out_csr_readdata(1) = '1') and not(data_buffer_valid = '1')) then
hps_to_fpga_read <= '1' ;
state := 1;
end if;
if (state = 1) then
-- zero the read request BEFORE the data appears
-- in the next state!
hps_to_fpga_read <= '0' ;
state := 2 ;
end if;
-- read the word from the FIFO
if (state = 2) then
data_buffer <= hps_to_fpga_readdata ; -- send back data
data_buffer_valid <= '1' ; -- set the data ready flag
hps_to_fpga_read <= '0' ;
state := 0 ; --6
end if;
-- =================================
-- FPGA_to_HPS state machine
--==================================
-- is there space in the
-- FPGA_to_HPS FIFO
-- and data is available
if (state2=0 and not(fpga_to_hps_in_csr_readdata(0) = '1') and data_buffer_valid = '1') then
fpga_to_hps_in_writedata <= data_buffer ;
fpga_to_hps_in_write <= '1' ;
state2 := 1 ;
end if;
-- finish the write to FPGA_to_HPS FIFO
--if (HPS_to_FPGA_state == 8'd8) begin
if state=1 then
fpga_to_hps_in_write <= '0' ;
data_buffer_valid <= '0' ; -- used the data, so clear flag
state2 := 0 ;
end if;
end if;
end process;
END behaviour;
Anyone with some more knowledge who can help me?
Thanks in advance
Maikel
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