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First vhdl design, building a bit memory

Mentz
Beginner
656 Views

Hi all,

I starting with vhdl, and build this first design,

Mentz_0-1599140515669.png

Than I wrote to a cyclone II device and got this:

Mentz_1-1599141084665.png

From this circuit, I was expecting that dff output goes high at DFF clock rising edge and stay high. But it goes low at clock rising edge even that clock signal doesn't feeds dff directly.

 

Could someone help with this? Any help apreciated.

 

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1 Solution
KhaiChein_Y_Intel
628 Views

Hi,

I tried to simulate the design; there is a spike in the DFF_Clock that causes the output of signal DFF_output as shown in waveform.PNG.

You may consider to remove the JK FF and AND gate.

 

Thanks.

Best regards,

KhaiY

 

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5 Replies
KhaiChein_Y_Intel
646 Views

Hi,

Could you share the design for investigation?What is the software edition/version you are using?

 

Thanks.

Best regards,

KhaiY

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Mentz
Beginner
640 Views

My software is:

Mentz_0-1599216924025.png

and attached, my design.

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KhaiChein_Y_Intel
629 Views

Hi,

I tried to simulate the design; there is a spike in the DFF_Clock that causes the output of signal DFF_output as shown in waveform.PNG.

You may consider to remove the JK FF and AND gate.

 

Thanks.

Best regards,

KhaiY

 

Mentz
Beginner
621 Views

Hi KhaiY,

 

I've changed my design, excluding AND gate and and some other changes and it worked,

thanks for your time and efforts

Mentz

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KhaiChein_Y_Intel
595 Views

Hi,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,

KhaiY


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