First vhdl design, building a bit memory

[Mentz]

Hi all,

I starting with vhdl, and build this first design,

Than I wrote to a cyclone II device and got this:

From this circuit, I was expecting that dff output goes high at DFF clock rising edge and stay high. But it goes low at clock rising edge even that clock signal doesn't feeds dff directly.

Could someone help with this? Any help apreciated.

[KhaiChein_Y_Intel]

Hi,

Could you share the design for investigation?What is the software edition/version you are using?

Thanks.

Best regards,

KhaiY

[Mentz]

My software is:

and attached, my design.

[KhaiChein_Y_Intel · Accepted solution]

Hi,

I tried to simulate the design; there is a spike in the DFF_Clock that causes the output of signal DFF_output as shown in waveform.PNG.

You may consider to remove the JK FF and AND gate.

Thanks.

Best regards,

KhaiY

[Mentz]

Hi KhaiY,

I've changed my design, excluding AND gate and and some other changes and it worked,

thanks for your time and efforts

Mentz

[KhaiChein_Y_Intel]

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best regards,

KhaiY