I starting with vhdl, and build this first design,
Than I wrote to a cyclone II device and got this:
From this circuit, I was expecting that dff output goes high at DFF clock rising edge and stay high. But it goes low at clock rising edge even that clock signal doesn't feeds dff directly.
Could someone help with this? Any help apreciated.
I've changed my design, excluding AND gate and and some other changes and it worked,
thanks for your time and efforts
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