I starting with vhdl, and build this first design,
Than I wrote to a cyclone II device and got this:
From this circuit, I was expecting that dff output goes high at DFF clock rising edge and stay high. But it goes low at clock rising edge even that clock signal doesn't feeds dff directly.
Could someone help with this? Any help apreciated.
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.