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Beginner
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Fitter doesn't assign HPS DDR3 pins

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Hi,

 

Im using the DE10 Nano SystemBuilder to create a projet.

 

I add the Cyclone V HPS in Platform Designer with the right SDRAM parameters (I tried with presets and from the datasheet) and generate.

 

I update my top module to connect the SOC System to the clock and memory pins.

 

I then add the .qip to my projet run Analysis & Synthesis and execute the pin_assignments tcl.

 

When I run the Fitter I get the error "Error (179000): Design requires 193 user-specified I/O pins -- too many to fit in the 145 user I/O pin locations available in the selected device" as if the memory pins were assigned to the user GPIO.

 

Any ideas where my mistake is (my projet is in attachment) ?

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Accepted Solutions
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Moderator
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First thing is that you had look into the wrong table, you should look into the table 11 U670 device, which only have 145 IO

 

second is that you have HPS inout pin that is not connected to the module, Quartus will not able to identify those pin are HPS thus it will assume it as the GPIO. This will cause it have more GPIO pin.

 

// inout       HPS_I2C0_SCLK,

// inout       HPS_I2C0_SDAT,

// inout       HPS_I2C1_SCLK,

// inout       HPS_I2C1_SDAT,

// inout       HPS_KEY,

// inout       HPS_LED,

// inout       HPS_LTC_GPIO,

// output       HPS_SD_CLK,

// inout       HPS_SD_CMD,

// inout    [3:0] HPS_SD_DATA,

// output       HPS_SPIM_CLK,

// input       HPS_SPIM_MISO,

// output       HPS_SPIM_MOSI,

// inout       HPS_SPIM_SS,

View solution in original post

12 Replies
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Moderator
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If you look into your pin assignment in the assignment editor. You already have 145 pin being assign with location. They are no more space for you to place the DDR. You need to revise your top level or use a larger device.
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Beginner
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Yes there is no more user GPIO (bank 3, 4, 5 and 8) but were can I assign HPS GPIO (bank 6 and 7) where my DDR is connected to ?

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Moderator
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Can you put the question more clear? Those GPIO pin I see in your design are floating. How do you intent to use those pin?

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Beginner
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Here the result of an example project I have :quartus_2019-05-23_11-25-25.png

As you can see the PIN locations where never assigned (I get the critical warning "No exact pin location assignment(s) ...") but the fitter somehow figured that these should be on the HPS GPIO.

 

If you question me about why I dont simply reuse that projet it is because its only assign HPS DDR GPIO and I want to know how to do so to assign I2C, UART, ... HPS GPIO.

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Moderator
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Have you go to assigment -> assignment editor to look for the location that you have set? change the category to location and you will see it.

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Beginner
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Yes I have and in my projet and the one working they aren't assigned. ​Moreover it is impossible to assign these by hand.

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Moderator
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you can disable it there or remove it from the assignment editor. Is there a concern doing it?

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Beginner
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No I can't the fitter location are not in the assignment editor they are generated when I execute the fitter ​but never saved in the projet. I starting to question myself have you ever used an soc fpga because you seem to consider the HPS as a fpga which is not.

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Moderator
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Those fitter location are automatically generated with the Top level design port that you have declared in the verilog code. If you see clearly, you have about 190++ pin declared, and out of it, the GPIO pin is not totally used:

 

//////////// GPIO_0, GPIO connect to GPIO Default //////////

inout   [35:0] GPIO_0,

 

//////////// GPIO_1, GPIO connect to GPIO Default //////////

inout   [35:0] GPIO_1

 

You only used it with

 

.uart0_rxd     (GPIO_0[0]),

.uart0_txd     (GPIO_0[1])

 

If you are not using so much, can you reduce it in your top level?

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Beginner
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In the Cyclone V Device Overview at page 13 you can see that my device has 288 FPGA GPIO and 181 HPS I/O.

In my design FPGA GPIO = ADC (4) + ARDUINO (17) + HDMI (35) + KEY (2) + LED (8) + SW (4) + GPIO_0 (36) + GPIO_1 (36) = 142 < 288 and HPS I/O = HPS* (120) = 120 < 181 in either case Im well below the limit.

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Highlighted
Moderator
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First thing is that you had look into the wrong table, you should look into the table 11 U670 device, which only have 145 IO

 

second is that you have HPS inout pin that is not connected to the module, Quartus will not able to identify those pin are HPS thus it will assume it as the GPIO. This will cause it have more GPIO pin.

 

// inout       HPS_I2C0_SCLK,

// inout       HPS_I2C0_SDAT,

// inout       HPS_I2C1_SCLK,

// inout       HPS_I2C1_SDAT,

// inout       HPS_KEY,

// inout       HPS_LED,

// inout       HPS_LTC_GPIO,

// output       HPS_SD_CLK,

// inout       HPS_SD_CMD,

// inout    [3:0] HPS_SD_DATA,

// output       HPS_SPIM_CLK,

// input       HPS_SPIM_MISO,

// output       HPS_SPIM_MOSI,

// inout       HPS_SPIM_SS,

View solution in original post

Highlighted
Beginner
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I read too fast you are right on the 145 GPIO.

I tried your answer and it works.

Thank you for your time and patience.

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