Flash programming issue with stratix kit development

[Altera_Forum]

Hi,

I have a stratix3 development kit.

Flash: 64 Mo

Max II

Stratix3 FPGA

USB blaster

I have designed a system with SOPC builder to execute the "web server" application on it. I want to stock the hardware and the software in flash memory. So, on power up the FPGA will be programmed and the software will execute on this SOPC system. However, I have an issue. I use the IDE mode to program flash but when I power off the board and then I power up, the FPGA isn't configured. I read the user guide "NIOS2 FLASH PROGRAMMER" but it doesn't help me to solve my issue. The problem may be due to "cpu vector address" or "offset address" for flash.

Reset Vector: Memory: ext_flash Offset: 0x20000 0x04020000

Exception Vector: Memory onchip_ram Offset: 0x20 0x00020020

I tryed to change them but I always have the same issue. 

I put the result of the programation of the flash memory: 

#!/bin/sh

#

# This file was automatically generated by the Nios II IDE Flash Programmer.

#

# It will be overwritten when the flash programmer options change.

#

cd C:/web_server/software/web_server_0/Debug

# Creating .flash file for the FPGA configuration

"$SOPC_KIT_NIOS2/bin/sof2flash" --offset=0x0 --input="C:/web_server/stratixIII_3

sl150_dev_niosII_standard.sof" --output="stratixIII_3sl150_dev_niosII_standard.f

lash" 

Info: ************************************************** *****************

Info: Running Quartus II Convert_programming_file

Info: Command: quartus_cpf --no_banner --convert C:/web_server/stratixIII_3sl150

_dev_niosII_standard.sof stratixIII_3sl150_dev_niosII_standard.rbf

Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings

Info: Peak virtual memory: 198 megabytes

Info: Processing ended: Tue Nov 03 18:57:38 2009

Info: Elapsed time: 00:00:05

Info: Total CPU time (on all processors): 00:00:06

# Programming flash with the FPGA configuration

"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x04000000 --sidp=0x00001098

--id=539028539 --timestamp=1257264267 "stratixIII_3sl150_dev_niosII_standard.f

lash"

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Resetting and pausing target processor: OK

Reading System ID at address 0x00001098: verified

: Checksumming existing contents 

00010000 : Verifying existing contents 

00018000 : Verifying existing contents 

00080000 : Verifying existing contents 

... 

...

00008000 : Reading existing contents 

00020000 : Reading existing contents 

00040000 : Reading existing contents 

00060000 : Reading existing contents 

Checksummed/read 5340kB in 135.9s 

00000000 ( 0%): Erasing 

00008000 ( 7%): Erasing 

00020000 (14%): Erasing 

00040000 (42%): Erasing 

00060000 (71%): Erasing 

Erased 448kB in 3.4s (131.7kB/s) 

00000000 ( 0%): Programming 

00008000 ( 0%): Programming 

00010000 ( 1%): Programming 

00018000 ( 1%): Programming 

00020000 ( 1%): Programming 

00040000 ( 3%): Programming 

00060000 ( 5%): Programming 

00080000 ( 7%): Programming 

000A0000 ( 7%): Programming 

000C0000 ( 7%): Programming 

...

...

00420000 ( 7%): Programming 

00440000 ( 7%): Programming 

00460000 ( 7%): Programming 

00480000 ( 7%): Programming 

004A0000 ( 7%): Programming 

004C0000 ( 7%): Programming 

004E0000 ( 7%): Programming 

00500000 ( 7%): Programming 

00520000 ( 7%): Programming 

00540000 ( 7%): Programming 

00560000 ( 7%): Programming 

00580000 ( 7%): Programming 

005A0000 ( 7%): Programming 

Programmed 5788KB in 15.9s (364.0KB/s) 

Device contents checksummed OK

Leaving target processor paused

# Creating .flash file for the project

"$SOPC_KIT_NIOS2/bin/elf2flash" --base=0x04000000 --end=0x5ffffff --reset=0x4020

000 --input="web_server_0.elf" --output="ext_flash.flash" --boot="C:/altera/90/i

p/altera/nios2_ip/altera_nios2/boot_loader_cfi.srec"

# Programming flash with the project

"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x04000000 --sidp=0x00001098

--id=539028539 --timestamp=1257264267 "ext_flash.flash"

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Resetting and pausing target processor: OK

Reading System ID at address 0x00001098: verified

: Checksumming existing contents 

00020000 : Reading existing contents 

00040000 : Reading existing contents 

00060000 : Reading existing contents 

Checksummed/read 41kB in 1.0s 

00020000 ( 0%): Erasing 

00040000 (33%): Erasing 

00060000 (66%): Erasing 

Erased 384kB in 2.6s (147.6kB/s) 

00020000 ( 0%): Programming 

00040000 (33%): Programming 

00060000 (66%): Programming 

Programmed 344KB +40KB in 20.9s (18.3KB/s) 

Device contents checksummed OK

Leaving target processor paused

# Creating .flash file for the project

"$SOPC_KIT_NIOS2/bin/elf2flash" --base=0x06000000 --end=0x7ffffff --reset=0x4020

000 --input="web_server_0.elf" --output="ext_flash_1.flash" --boot="C:/altera/90

/ip/altera/nios2_ip/altera_nios2/boot_loader_cfi.srec"

# Programming flash with the project

"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x06000000 --sidp=0x00001098

--id=539028539 --timestamp=1257264267 "ext_flash_1.flash"

Empty flash content cannot be programmed or verified

# Creating .flash file for the read only zip file system

"$SOPC_KIT_NIOS2/bin/bin2flash" --base=0x04000000 --location=0x0 --input="C:/web

_server/software/web_server_0_syslib/ro_zipfs.zip" --output="rozipfs.flash"

# Programming flash with the read only zip file system

"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x04000000 --sidp=0x00001098

--id=539028539 --timestamp=1257264267 "rozipfs.flash"

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Resetting and pausing target processor: OK

Reading System ID at address 0x00001098: verified

: Checksumming existing contents 

00000000 : Reading existing contents 

00008000 : Reading existing contents 

Checksummed/read 26kB in 0.7s 

00000000 ( 0%): Erasing 

00008000 (50%): Erasing 

Erased 64kB in 0.7s (91.4kB/s) 

00000000 ( 0%): Programming 

00008000 (50%): Programming 

Programmed 39KB +25KB in 3.6s (17.7KB/s) 

Device contents checksummed OK

Leaving target processor paused

Thank you for your help,

Best regards,

Jeremy.

[Altera_Forum]

Did you take into account the information provided on page 2-19 of the reference manual. Apparently there is a rotary switch that needs to be set accordingly. Also, you need to make sure you program the FPGA configuration and your software image into the appropriate location within the flash. It looks to me like you're trying to program the FPGA image, software image, and read-only zip filesystem all into the same location in the flash. Not going to work. 

 Jake

[Altera_Forum]

Hi, 

 Thank you for your answer. Rotary switch are OK. Indeed, I can stock FPGA configuration file in the flash memory by the mean of Quartus plus a design included in the design kit "stratixIII_3sl150_dev_pfl" (flow is described in documentation entitled : Programming the flash device).  I think your second sugestion is the right. Indeed, I want to stock all these files. I am a beginner in digital electronic ( I'm working in analog electronic). So could you explain me why is not going to work please ?  For my part I 'm going to read again the documentation.  Best regards,  Jeremy.