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Hi Kimi,
Apologize that it cannot be. The reason is because some of the I/O Banks are inter-related.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_gpio.pdf
Thank You.
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Are there any I/O banks that are not inter-related in 10M50DAF484?
If so, what about I/O banks that are not inter-related?
Thank you
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Hi Kimi,
Apologize it cannot be. Another thing to take note is that the VCCIO is required for the device to boot up. During device boot up, all VCCIO banks must reach the recommended operating level before configuration completes.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_pwr.pdf (Page 8)
Thank You.

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