FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

Fpga in the loop - DE4 board

Altera_Forum
Honored Contributor II
1,146 Views

Dear all, 

 

I'm using the "HDL verifier" toolbox provided with Matlab to stimulate a board equipped with FPGA directly from matlab. 

This technique is generally known as FPGA in the Loop simulation or FIL. 

 

The HDL verifier I use supports standard ethernet interfaces to exchange data with the board. 

The supported interfaces are GMII, RGMII and MII GMII, RGMII and MII. 

 

This is ok for the DE2 boards. 

 

The DE4 board, however, implements the SGMII mode that seems not to be supported by HDL verifer. 

 

Do you have any suggestion on: 

1) does an HDL verifier version that supports SGMII exists? 

2) how to use a DE4 board in a FPGA in the loop simulation (maybe not using HDL verifier)?
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
106 Views

When I last looked into HIL with Matlab, the answer was they currently only supported Xilinx boards. This was about 2 years ago, so they may have added Altera support. I suggest you contact Mathworks.

Reply