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Altera_Forum
Honored Contributor I
761 Views

Frame Reader configuration

Hi, 

I use DE2 board and TERASIC TRDB_LTM (800x480 Touch LCD) 

I attempt to build the following configuration: 

NIOS2 that runs the program from SRAM: Works 

LCD that is connected to Video Clocked Output IP that is fed from Frame Reader that reads the data from DE2 SDRAM. 

The Video interface is configured to 3 planes 5 bit each, parallel. with resolution that is the same as the LCD. 

 

If i connect Test Pattern Generator instead of Frame Reader, then i get the pattern. 

 

If i connect Frame Reader I fail to get any picture. 

 

I'm not sure regarding the configuration of the Frame Reader. 

 

The SOPC configuration of the Frame Reader: 

16 bit port. 

max width:800 

max height:480 

parallel planes: 3 

serial planes: 1 

bits per color plane: 5  

 

As far as i understand the configuration, there is 1 cycle per word. 

so words per frame= cycles per frame=800*480=384000 am i correct? 

what should i set in the interlacing register (i want to hold all the frame in one place)? 

any insights regarding SDRAM configuration on DE2 board? (although i think it works fine) 

 

Thanks in advance.
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3 Replies
Altera_Forum
Honored Contributor I
53 Views

hi there, 

 

in the video imaging user guide is written the maximum size of the frame is 640X480, u should use a scaler if want a bigger picture... 

 

im also trying to run the frame buffer with nearly the same configurations but i also cant get an image. 

 

greets
Altera_Forum
Honored Contributor I
53 Views

I was able to get an image using the example from this thread: 

http://www.alteraforum.com/forum/showthread.php?p=83223 

i just changed the connections of the example to GPIO that i used for the LTM device.
Altera_Forum
Honored Contributor I
53 Views

use the frame reader in my design with the following settings: 

Bits per pixel per color plane: 8 

Number of color planes in parallel: 3 

Number of color planes in sequence: 1 

Maximum Image width: 1920 

Maximum Image height: 1080 

Master port width: 64 

Read master FIFO depth: 1024 

Read master FIFO burst target: 64 

Use separate clock for the Avalon MM master interface: unchecked  

Kindly confirm if the following calculations for number the words and the Single Cycle Color Patterns are true or not 

1- // Words 

IOWR(FRAMEREADER_BASE, 5, 259200); // (1920*1080*8*3)/48= 1036800 

 

2- // Single Cycle Color Patterns 

IOWR(FRAMEREADER_BASE, 6, 2073600); // 1920*1080=2073600 number of pixels in the frame
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