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Altera_Forum
Honored Contributor I
1,785 Views

Frame reader initialization

Hello, 

 

I know there is already a lot on the forum about the Frame reader from the VIP suite, but I still don't get it running. I used the memtest software example to test the DDR Ram module of my Cyclone III Nios II evaluation kit (LCD 800 x 480 pixels) and it worked perfectly, so the harware design seems OK. 

 

I've implemented a Frame reader in the design (the same design with the test pattern generator works perfectly, so I think it must be the C-code for the initialization that contains some errors...). I want the LCD to display a complete white image, but the screen stays black. 

 

Here is the main.c file: 

 

#include <stdio.h># include <unistd.h># include <stdlib.h># include <string.h># include <ctype.h># include "system.h"# include <stdio.h># include <io.h> typedef struct { unsigned int framebuffer; }display_buffer; int main(void) { display_buffer buffer; //Make a White background int xctr=0, yctr=0; for( xctr=0; xctr<800; ++xctr ) { for( yctr=0; yctr<480; ++yctr ) { buffer.framebuffer = 0xFFFFFFFF; } } //Frame 0 base adress IOWR(ALT_VIP_VFR_0_BASE, 4, &buffer.framebuffer); //Select frame 0 IOWR(ALT_VIP_VFR_0_BASE, 3, 0); //number of words for frame 0 (800*480)=384 000 IOWR(ALT_VIP_VFR_0_BASE, 5, 384000); //color cycles for frame 0 (800*480) // see http://www.alteraforum.com/forum/showthread.php?t=20596&page=2 IOWR(ALT_VIP_VFR_0_BASE, 6, 384000); // Frame 0 Reserved IOWR(ALT_VIP_VFR_0_BASE, 7, 0); //Frame 0 width IOWR(ALT_VIP_VFR_0_BASE, 8, 800); //Frame 0 Height IOWR(ALT_VIP_VFR_0_BASE, 9, 480); // Frame 0 Interlaced IOWR(ALT_VIP_VFR_0_BASE, 10, 0); //Start Frame Reader IOWR(ALT_VIP_VFR_0_BASE, 0, 1); printf("Frame reader initialized"); while(1); return 0; }  

 

Any suggestions? 

 

Thanks! 

 

Best regards, 

 

Hans
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18 Replies
Altera_Forum
Honored Contributor I
178 Views

I know it's perhaps a very stupid mistake I made, but maybe it would help if I added the complete project as a ZIP file, so here it is. 

 

Thanks again! 

 

Best, 

 

Hans
Altera_Forum
Honored Contributor I
178 Views

Hi, it's me again. Have you tried using the SP2 for Quartus? There could be a patched FrameReader in the SP. Perhaps this solves the issue that the IRQ is not working correctly. I could not try it here at work, because we still use an older version. 

 

If I find some time (perhaps to the weekend) I will test some more, somehow this issue don't let me go. 

 

Have a nice day!
Altera_Forum
Honored Contributor I
178 Views

For everyone who is interested, we discussed the issue and I think there are four possible error sources: 

 

1. The interrupt of the FR does not work in SP 1 or earlier correct, so you will have to add a patch to the Reader. 

 

2. Perhaps there are some TimingProblems in the Design. 

 

3. The Frame Reader uses burst reads. So the DDR SDRAM Bridge does not support them in the configuration. Perhaps the video stream is running out of data because of this. 

 

4. The implementation in the Nios EDS could be wrong. Perhaps the addressing of the buffer is not correct. 

 

Would be nice if anyone could prove or dissaprove some of this issues or add to the list. Thanks.
Altera_Forum
Honored Contributor I
178 Views

Hi, have you got the link to the post where you found it? Thanks.

Altera_Forum
Honored Contributor I
178 Views

Altera_Forum
Honored Contributor I
178 Views

I do not have the time right now, to look into the example, but I tried this yersterday at my testing. 

 

I have attached a picture of the modifications I made to the SOPC-system. I added a FrameBuffer, which I configured to use the same read burst and master bit width to access the DDR SDRAM in the design as your FrameReader. As I run this system on the neek it worked quite fine and gave me the testpattern. I had also configured the FrameBuffer to not add or throw away frames, so normally if the stream would have run out of the specification I expected the LCD image to be altered, too. 

 

I am curious what you get out of the project when you carry over the design from the example you found.
Altera_Forum
Honored Contributor I
178 Views

Hey, 

 

Thanks again for the reply, I will test the example in my project as soon as I can, but I had to format my entire PC to setup a RAID system, and now NIOS IDE seems to have some troubles finding the include files in the Altera.components folder. So it will take some time until I'm completely up and running again. But I'll post when I got some results! 

 

Best, 

 

Hans
Altera_Forum
Honored Contributor I
178 Views

Hi Hans, 

 

sorry but I think the design example you found will not bring you any further with your problem. I had some time yersterday evening and looked into the example and your code again. I then decided to put that all aside and program an example from scratch. So I started with the "standard" design example from the Nios Evaluation Kit CD v8.0 and implemented FrameReader and Output to the LCD by using the LCDVideoSyncGenerator. With a bit of tweaking after my first try (I typed one declaration wrong) I had a design. I then created some NIOS Code where I have read back the written data to be able to verify, that all registers and Ram is set right. This example works well, except the problem I had with some of my projects before, that the LCD is flickering heavily. (mixing VIP with VideoSyncGenerator => Avalon Video Protocoll vs. Avalon Protocoll) 

 

I then also tried to implement the IP Core using the Clocked Video Output in my new created design, but then I got no output at all. Then also I ran out of time, because even I must sleep sometimes ;-) I took your first code of experiment5 again and replaced the CVO against one LCDVideoSyncGenerator. I really expected that to work. I created a new Nios Project and used my code from the other now running project. in the bsp Editor I edited everything, so that the whole code is run and stored in the ssram. Unfortunately I got nothing out of your design again, perhaps there is some fault in the pinning or anything like that. 

 

Feel free to further investigate this issue, I have attached my testsystem to this thread for you. I thought once more about it and I think you could try to implement the CVO together withe the FrameReader. Perhaps there was just something with the pinning not right, as I tested the system, because my verilog is not so good. 

 

Good luck, yours Peet. 

 

(Please be aware, it's a RAR-File although the fileextension says .zip)
Altera_Forum
Honored Contributor I
178 Views

Hey Peet, 

 

Thanks for the example design. I studied it for a few hours today but I must confess that I don't get NIOS IDE to Run it properly... I never get an image, the programs says the "Program running, wait!" line, and then it sort of dies. I have a feeling it has something to do with the include paths (altough the project builds properly, I saw you have a drivers directory and a HAL directory included in your bsp directory). But I have no real clue (the NEEK is fine, because I see the ALTERA logo every time I start it up ;) ) what that problem could be (I'm not a specialist in NIOS or Eclipse, I must confess) 

 

On the other hand I have some good news for the hardware, after looking at your SOPC project, I noticed that you configured the FR to output 3 color planes in parallel, and I saw the configuration of the VCO, which also had the parallel option on. I would change this to 3 planes in sequence (in the VCO and FR), because the VCO just outputs the data in the same format he gets it in, when it's parallel he outputs parallel data, when it's a sequens, he outputs a sequens. And the MAX II chip expects sequential data. I tested this with a standard TPG -> CVO setup and the symbols prooved my theory. My new theory I cannot test because I can't get the standard program to run properly... 

 

I have a bit of a feeling that I really let you down by having such stupid problems (why I cannot run your software properly...) although I tried every tutorial Altera is offering on their website... I'm really sorry for that. 

 

Thanks again for all your help! 

 

Best, 

 

Hans
Altera_Forum
Honored Contributor I
178 Views

Or it could have to do with the settings of the linker script. I use an auto generated in NIOS IDE and all settings (Program memory, ...., Heap, stack) are set to ddr_sdram which is probably also not the way it should be... 

 

Best, and sorry again! 

 

Hans
Altera_Forum
Honored Contributor I
178 Views

Hi there. It's not a problem. Here are some tipps to get that NIOS Code running. First to tell you, you are totally right. The Nios EDS codes many paths hard into the bsp. I also have problems with that every time I get a project from a colleague. 

 

My way (perhaps not the best way, but it works) is to generate a totally new Nios Project. Generate it from template, with bsp. I always take "hello world" as template. When the generation is completed, you will have to edit the bsp settings. In the first tab you chose the ssram for the two stacks. Then in the linker tab you set every property to ssram. After that generate the bsp. 

 

Now the last thing to do is open the previous c-code file in your favorite editor and past and copy the code over to the new hello world c-file. When you then compile the whole code it should work fine with my synthesized system. 

 

I will also have some sparetime over lunch, where I will test your hint with the sequential transmission. I really never thought about that, also not read it in any documentation I think, but that seems to make sense. Will have to try that on the hardware. 

 

(btw. it's not your problem, that I bite something like this question so much. This even helps me very much, because when we get that system to work with the CVO it will help me for an old project. So don't let yourself wear down by it.) ;-) 

 

Yours, Peet.
Altera_Forum
Honored Contributor I
178 Views

Hey Peet, 

 

I spent the whole afternoon trying stuff out. First of all I'll start with another dumbass question ;) , I was able to set up the "NIOS Software build tools for Eclipse" software instead of the NIOS IDE, it is indeed much handier to import projects and the projects themself are much better organised (to my feeling). The only problem is that I don't have a "Run as NIOS II hardware" option available, I only have a "Run as local C/C++ application" option. Probably still something wrong with the basic settings somewhere. Any hints (I run the SP2 version of the NIOS software)? But I was able with the flash programmer to test your design (but then I can't use the console to view printf messages, so now running or debugging possible from the NIOS software), and indeed it flickers, so I used the VCO instead and also I got no picture. 

 

Now I looked again at the other example (for the CIIIc120 board) and discovered they activated the "use control port" option on the VCO as well and they initialized the VCO after the frame buffer. So I activated it, connected it to the data master of the CPU and wrote some basic settings into the control registers. I still got no picture, but when I can run/debug from within NIOS, then I can check the status registers of the VCO using simple printf messages (but for now I can't see any printf messages of the software because I cannot run it from NIOS), because then we can see if the VCO is outputting data or not. 

 

Another thing that's done in the example is they set the FIFO underflow bit again (they say it's not necessairy but they set it anyway...). I tried it here, but no direct succes without debug option. 

 

BTW, for the neek daughter card manual use this link: 

http://www.terasic.com/downloads/cd-rom/mtdb/ 

There you can download all the documentation for the daughter card and it includes a pdf where you can find all the info about the MAX chip, LCD data for the VCO and VGA data,... might be handy. 

 

I have a feeling succes is not far away.... :cool:  

 

Thanks and take care, 

 

Best, 

 

Hans
Altera_Forum
Honored Contributor I
178 Views

Hey Peet, 

 

Don't bother about the "run as" configurations, it seems to have something to do with the windows 7 x64 release. Some compatibility issues, I'm now reinstalling the entire altera software with the help of another forum thread. 

 

I will be away for a big part of the weekend to play concerts, but I hope to investgate some more in our issue next week. By then all those minor software problems on my side will be solved, normally. 

 

Take care and enjoy the weekend!:cool:  

 

Best  

 

Hans
Altera_Forum
Honored Contributor I
178 Views

Hey Hans, 

 

Perhaps we should erase all other components that uses IRQs from the system. There is one thread here in the forum, where they had problems with the uart in this case, but I did not find it again. 

 

I tried the system on friday, but hadn't the time to reply. Same as you, I am out and and do much on the weekends. Hope your concert went well. So I think the system flickers one frame, but then stops. It is very short and I can't see it every time. I thought about, what would happen, if there is a FrameBuffer after the FrameReader. The Buffer could repeat the Image when it's buffer runs out, so there will be a way to see what it shows in the first frame. I have not tried that, but it might be interesting. Problem there will be, that the FrameReader and FrameBuffer must share the ddr ram for this. 

 

I will not have much time next week, but perhaps you find out something more. Good luck!
Altera_Forum
Honored Contributor I
178 Views

Hey Peet, 

 

I was experimenting some more this afternoon and I realized that we will need to take one step back and look again at the hardware setup. I didn't get the STATUS register of the VCO to a "1", this happens when the VCO is outputting correct data. I will check this in detail tonight using signaltap. 

 

So I changed the SOPC settings again, I added a test pattern generator and connected it straight to the VCO (I switched off the control bus again, so also no IRQ problems anymore) and disabled the FR. But still I got no image, normally in this setup we need a nice test pattern as you can see in Experiment3 I added in the attachment. This is the most simple form to use the VCO and TPG, and here it works perfectly. A cause of the problem can be: 

 

-The timing problems we get when the design builds (the current design is more complex then Experiment3, so maybe better constraints needed?). This could be solved by adding the "alt_vip_cvo.sdc" file to the timequest list (when there's a problem with the VCO constraints). This file is included in the IP directory of altera, and sets the timing constraints for the VCO. But when I add this file to the project, timequest ignores all the false path settings because of some error in the sdc (I'm not very good in sdc language so I wasn't able to implement it correctly...). They used this sdc file also in the example for the C3C120 board we shared earlier in this thread. 

 

It's just after some thinking I came to this conclusion, I have no idea if it can help us to solve the problem... 

 

Best and talk soon! 

 

Hans
Altera_Forum
Honored Contributor I
178 Views

Hi Hans, 

 

I added the TPG again and deactivated the FR. Worked here right without touching anything else. Setup and Hold timings are ok, rest is violated. I have only the clocks constrained. 

 

When I add the FR again and connect to the CVO it does not work, but the flicker is still there. So if you like try to step into your idea, I will first try to get out of the system what he is transmitting in the first frame. 

 

We will see...
Altera_Forum
Honored Contributor I
178 Views

Hey Peet 

 

I put a lot of efford in our design yesterday. I'm still investigating in the configuration of the CVO, because I think it is necessary it uses its control port in combination with the FR (I see it on every example I found).  

The reason is the following:  

 

The clocked_video_out works perfectly, so the FR is outputting good data. But when we connect the VCO, everything dies (although both output modules work perfectly with the TPG). So I read all the documentation again and tried to setup the VCO trough the control port. Which didn't succeed yet. I also posted a reply in our names to a thread which was investigating in the control port of the VCO (I hope you have no problem I used your name as well...). 

 

here is the link of the thread: 

 

http://www.alteraforum.com/forum/showthread.php?t=4884&page=3 

 

I hope to have some better news for you soon... 

 

Best, 

 

Hans
Altera_Forum
Honored Contributor I
178 Views

The Solution to this problem can be found here: http://www.alteraforum.com/forum/showpost.php?p=90774&postcount=32 

 

mr_DK solved the problem. Nice work! :D
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