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Altera_Forum
Honored Contributor I
753 Views

HPC II in Stratix III DSP kit: mem_clk[0] is not accepted as Bidir

Im using the HPC II to control the DDR2 1GB DIMM that comes in the Stratix III DSP kit. Ive done the tutorial well, but when i include the controller in my design the fitter responds with the following error: 

 

Error: Differential I/O standard LVDS cannot be used on the Bidir pin mem_clk[0] 

 

Ive tried to change the "Treat Bidirectional Pin as Output Pin" option for this pin, but it didnt work also.  

 

Iv also checked the Warnings and Infos of the example and found there an info saying that the quartus was converting the pins mem_clk[0] e mem_clk_n[0] to output pins because the physical pin doesnt support LVDS Bidir. 

 

Since these signals are made by the mega-wizard, i couldnt find a way to change them to OUT pins.  

 

What can i do do fix this? 

 

thanks
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2 Replies
Altera_Forum
Honored Contributor I
48 Views

Altera DDR2 RAM controller are not intended to use LVDS IO-standard. The suggested standard is SSTL-18 CLASS I.

Altera_Forum
Honored Contributor I
48 Views

Thanks, i think it solved the problem.

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