I started studying the Cyclone V SOC, and I have few questions:
1- According to benchmark doc: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/ds_nios2_perf.pdf
NIOS II/f = 170MHz; NIOS II/e = 210MHz.
Why NIOS II/f is slower than NIOS II/e ?
Isn't it suppose to be the opposite ?
2- In Quartus II when I write the C program in Main ( ) I do it after launching NIOS II software build tool. So, this means my software will run on the NIOS II 210MHz processor. How can I make it run on the HPS which has ARM processor with speed = 925MHz ?
3- So far all the docs I have seen for Cyclone V were hardware. Is there some kind of programmer reference docs anywhere so I could use it in my C program ?
1) The column headers in that document must be swapped.
2) You must use the EDS and DS-5 tool flow to write and compile a design for an HPS. While Nios and HPS flows use Eclipse as a base, the tools are different.
3) Not sure how you missed all this: https://www.intel.com/content/www/us/en/programmable/products/design-software/embedded-software-deve...
You can also start with this training: