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HSMC interface IO in SOPC Builder

Altera_Forum
Honored Contributor II
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I have a Cyclone III Starter kit, and I want to write some datas in dr_sdram memory from HSMC IO. 

 

In SOPC Builder, how do I build this interface HSMC IO( LVDS format) ? 

Do I use the RapidIO megacore or GPIO ?
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Altera_Forum
Honored Contributor II
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it depends on what is connected to the HSMC connector. Do you use a standard interface? (LVDS is just a voltage level)

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Altera_Forum
Honored Contributor II
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yes, standard interface

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Altera_Forum
Honored Contributor II
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what interface? what protocol? We can't help you without more details.

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Altera_Forum
Honored Contributor II
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My project' application is in ultrasound area. High speed is necessary. 

 

I will give the datas from an ultrasound kit (AFE5805 - Texas). It sends 12 bits serial in LVDS format, I transform them to parallel format and the Cyclone III Starter kit' job is receive and process the ultrasound signal. 

 

I use now the standard example for to write and to read in DDR-SDRAM memory, and the next step is add this IO.
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Altera_Forum
Honored Contributor II
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So what you need is a component that does the serial-to-parallel conversion and present the data in a way that can be understood by the Nios CPU. I don't think that such a component already exists (but I could be wrong), so you'll probably have to create your own custom component. 

I would recommend that this custom component presents the parallel data using the Avalon Stream protocol. It is very easy to implement, and you'll be able to use SOPC builder ready available components to handle the actual transfer to memory (a double clocked fifo and a sgdma, as an example).
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Altera_Forum
Honored Contributor II
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Interesting...I can use this later. 

I use now a kit ADSDESER (texas too) that converts serial to parallel. 

 

My first question is my easy: 

 

How I found the correct address of HSMC pins in a SOPC project, using GPIO for example ? 

I saw the system.h file, and I found the led_io and button_io only. 

 

I pretend read the ddr-sdram memory, and I would to see the result in a array of leds from hsmc output pins, not leds of the FPGA kit.
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Altera_Forum
Honored Contributor II
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You need to add a PIO to your SOPC hardware project first, then update the top level design file to connect those to external pins, and then use the assignment editor to set the exact pin used for each signal. I would recommend to look at the board schematic rather than the documentation to find out which FPGA pin is connected to which pin on the HSMC connector. Altera's kit documentations are known to have a few mistakes in them. 

With the new SOPC system, when you regenerate the system library you'll see your new PIO port in system.h 

 

I'm not sure that a PIO is the best solution though, it is rather slow.
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Altera_Forum
Honored Contributor II
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Thank you Daixiwen, 

 

I add the PIO in project. 

But the standard example doesn't have the top level design file (.bdf) I can't update this... 

Will I create a new file ?
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Altera_Forum
Honored Contributor II
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No, I guess the top level file is a verilog file (.v extension). You can either edit that file or recreate everything in a .bdf file (but this last option will take some time...)

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Altera_Forum
Honored Contributor II
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Thank you Daixiwen. 

 

I add a GPIO (12 pins) in my project and modified the verilog file. The program has been successfully compiled. I do the pin assigment using the HSMC debug header. 

 

But, when I run the program in Nios, nothing happen in the output pins. 

(for example, I would to write 0x07 in the new GPIO) 

Aways the output pins are in high level (2.5V). 

 

Somebody can help me ?
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

int main(void) 

int buttons; 

MenuHeader(); 

while (1) 

buttons = IORD_ALTERA_AVALON_PIO_DATA(BUTTON_PIO_BASE); 

 

IOWR_ALTERA_AVALON_PIO_DATA(PIO_BASE,0x08); 

 

IOWR_ALTERA_AVALON_PIO_DATA(LED_PIO_BASE,buttons); 

return (0); 

--- Quote End ---  

My Nios'code: PIO_BASE is the hsmc output.
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Altera_Forum
Honored Contributor II
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Check that you assigned the ports to the correct FPGA pins on the pin planner. 

You can also use a signaltap probe on the ports that you added to check if you are setting them to the correct value. From the code that you posted. it seems that you do.
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