Hello, Could anyone please explain and provide some resources, about how trustworthy is the code, automatically generated from a .bdf file in Quartus.

[Vicky1]

hi,

It`s Quartus feature & It will generate the HDL code as in context to HDL support to Quartus tool. If you came across any unexpected behavior with this feature please share here with details like screenshot, code snippet etc.

Regards,

Vicky

[NShan12]

Hello Vicky,

Thanks for your answer. I havent come across any unexpected behaviour yet. But, that's the question, is there a possibility of unexpected error when complex schematics are converted to VHDL? How reliable is the VHDL code generated automatically from schematic? I am deciding if I should allow the tool to auto generate the VHDL or understand the schematic and manually design(expensive in terms of time). I am also asking this, keeping in mind the certification and qualification of mission critical aerospace products. I tried this on few example schematics and the generated code is quite confusing and not easy to understand.

Your suggestions would be really helpful.

[Vicky1]

Hi,

"is there a possibility of unexpected error when complex schematics are converted to VHDL? How reliable is the VHDL code generated automatically from schematic? I am deciding if I should allow the tool to auto generate the VHDL or understand the schematic and manually design(expensive in terms of time). " ------- There is no issue recorded as such. If you allow to the tool to generate HDL, then tool will generates as per the algorithm inbuilt within it. The level of abstraction of the code generated by tool will be mostly behavioral, less visible & accessible to outside world as compared to manual design style.

Thanks,

Vicky

[NShan12]

Hello Vicky,

Thank you for your reply.