Hello, May I ask was your problem solved? How did you solved it. Thank you very much.

[AlHill]

What problem?

Doc

[User1580871742356367]

Hi Al,

First of all, very much appreciated your response.

I have Arrira 10 SoC FPGA and ADC12DJ3200 with 8 lanes of JESD204 Rx. ADC sampling clock is 3GHz and FPGA device clock is 300MHz with SYSREF at 3GHz/640.

I'm having the problem that dev_sync_n stays LOW even if FPGA has received x"BCBC" and rx_is_lockedtodata are HIGH from ADC chip. So ADC won't send data.

What would be your suggestions on this. Thank you very much.

[AlHill]

No suggestions from me. It is just that you did not state what the problem was in the original post.

Now, with the problem defined, someone can help you.

Doc

[Nathan_R_Intel]

Hie,

There could be a multiple reasons why this is happening. Basically, if ADC has asserted sync_n and send K28.5 to FPGA, the FPGA will send out dev_sync_n as high.

Hence, please use signal tap to check if sync_n is asserted high correctly when Receiver is receiving K28.5 characters.

Please refer to chapter 6 of the JESD user guide which shows how to debug this issue.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf

Do let me know if there is further questions.

Regards,

Nathan

[User1580871742356367]

Hi Nathen, #1 1. There will be no SYNC_N asserted by ADC. The SYNC_N is a input at ADC (from FPGA JESD204B Rx to ADC). 2. SYNC_N = dev_sync_n, is generated by FPGA JESD204B Rx link layer. 3. FPGA will dessert dev_sync_n once it received 4+ consecutive K28.5 (x”BC”), which means dev_sync_n will be ‘1’ so as SYNC_N #2 1. My current issue is that FPGA re-assert dev_sync_n (SYNC_N) after a while(??!) 2. After FPGA re-assert dev_sync_n (SYNC_N), ADC is sending K28.5 again, however, 3. FPGA won’t responding it anymore unless gets reset. Which means, 4. I’ll have to a reset again and then again . . . #3 Could not find useful debug info from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf So that I’m seeking for the help from the Community! Thank you very much. Regards, Ying

[Nathan_R_Intel]

Hie Ying,

Your description of the problem statement is confusing. You need to describe the problem clearly for the community or Intel forum Application Engineers to understand your issue and provide suggestion. Your points described in #1 is known. After reading your point #2 is only when I can understand your issue. 

Your problem statement is FPGA re-assert dev_sync_n during run time after CGS. Hence, this seems like you need to check the Converter settings configured in the FPGA and ADC. Also check the clocking and SPI register settings related to conveter are correct. Also if you are using subclass 1, then ensure the sysref generator is configured to generate sysref pulse, sysref pin assignment and polarity on board is correct and there is missing sysref pin between FPGA and IP core's port.

Regards,

Nathan

[KeenYewL_Intel]

Hello Ying, may i know if you have further inquiry to this thread? If you do, please provide the detail here so we can follow up. Thanks.