Hello, community, what is the correct pinning of the 10CX085YU484 FPGA. The 10CX085.OLB schematic symbol from Intel shows a difference at pin H2, J1 , K2 and K3 in comparison to the Device Pin-Out-File 10cx085.xls. Is the .OLB file just obsolete?

[MSchw39]

 H2 (VREFB3BN0), J1 (VCCIO3B), K2 (VCCIO3B) and K3 (VCCIO3B) in 10CX085.OLB 

H2, J1, K2, K3 are GND in the 10CX085.xls file.

[AR_A_Intel]

Hi

This is due to version revised, pin changed VCCIO3B and VREF3BN0 to GND pins in Pin List U484. We will schedule to add-in package U484 in next, probably we would need 5days turn-around-time.

[AR_A_Intel]

We send you an email on update for pinning of the 10CX085YU484 FPGA