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Altera_Forum
Honored Contributor I
1,071 Views

Help with Santa Cruz to HSMC Converter

board: 

CIII DSP Development Kit 

daughtercard:  

Bitec Santa Cruz Camera (Uses ov5620 chip) 

interface:  

Terasic Santa Cruz to HSMC Adapter board (THDB-H2S) 

 

The camera is firing up fine. I can see the input signals and pixel clock through the SignalTap LA. However, when I try to communicate with it over I2C, the messages tend to either take seconds to complete or hang indefinitely. 

I am using an example design originally programmed for a CII DSP Dev kit but modified for the CIII pinout which I have triple checked. 

 

The Terasic converter uses bidirectional level converters to interface the 2.5V off of the CIII DSP board to the Santa Cruz camera. 

 

I am running out of ideas as to what could be causing these problems with the I2C. Has anyone else any experience with this converter board?
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6 Replies
Altera_Forum
Honored Contributor I
40 Views

Hi, just suggestion: 

in HSMC connectors the I2C bus ( along with JTAG ) are special IOs, not along with others general PIOs. their place also differs among male and female connector. 

 

 

does Santa Cruz behave like this too? why you don't try to put the I2C through other PIOs?
Altera_Forum
Honored Contributor I
40 Views

 

--- Quote Start ---  

Hi, just suggestion: 

in HSMC connectors the I2C bus ( along with JTAG ) are special IOs, not along with others general PIOs. their place also differs among male and female connector. 

 

does Santa Cruz behave like this too? why you don't try to put the I2C through other PIOs? 

--- Quote End ---  

 

 

The SC adapter board reserves the I2C pins off of the HSMC connector for a storage element.  

I am currently using the pins corresponding to the cameras serial data/clock which are hardwired through the Santa Cruz interface to regular PIO pins on the HSMC. 

Unfortunately this leaves me little options in terms of rewiring these pins unless I can come up with my own special adapter to sit between the Cyclone III board and the SC adapter board so as to redirect the HSMC I2C to more suitable pins. Has anyone any suggestions?
Altera_Forum
Honored Contributor I
40 Views

Apart from using a suitable logic level, I2C requires also strong pull-up resistors and a bidirectional level-translator at least for SDA. This isn't a matter of using a particular FPGA I/O pin but of a right hardware design with the HSMC to Santa Cruz adapter. I can't see from your post, if the I2C requirements are met.

Altera_Forum
Honored Contributor I
40 Views

 

--- Quote Start ---  

Apart from using a suitable logic level, I2C requires also strong pull-up resistors and a bidirectional level-translator at least for SDA. This isn't a matter of using a particular FPGA I/O pin but of a right hardware design with the HSMC to Santa Cruz adapter. I can't see from your post, if the I2C requirements are met. 

--- Quote End ---  

 

 

This is strange, I was told repeatedly from multiple sources that I2C required WEAK pull-up resistors. Perhaps this changes with the alternate interface? The level translators are bi-directional and should not be the problem. 

Thanks
Altera_Forum
Honored Contributor I
40 Views

I would classify I2C resistors as strong pull-up, a usual value is 1 to 5 k. Possibly the used bidirectional level translators are able to produce valid I2C level at both sides, but I'm not sure about. Without knowing the adapter board schematic, I can only guess. A simple way would be to check the waveforms with an oscilloscope.

Altera_Forum
Honored Contributor I
40 Views

I know this is an old post, but did you ever get this working? 

 

I saw your posting on altera forums. I'm having similiar issues. It seems SDA and SDC are not being pulled up through the level translators?? 

 

Jacob