Help with design!!!!!

[Altera_Forum]

What we are trying to do is develop a circuit that will have the following parameters: 

 6-inputs, 8 outputs  I1 I2 IB1 IB2 IB3 IB4 O1 O2 O3 O4 O5 O6 O7 O8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0  1 0 0 0 1 0 0 0 1 0 0 0 0 0  1 0 0 0 0 1 0 0 0 1 0 0 0 0  0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1  I/IB = Inputs O = Outputs There will also be clocks that are involved with the design because the outputs will need to go high when the correct conditions happen. However, after a period of time, we will need to have those high outputs go low. I will attach what I have so far. We tried implementing j-k flip flops, however those produced two high outputs, one of which we don't need. If anyone can help me it would be greatly appreciated!!!!

[Altera_Forum]

For some reason the outputs don't correspond with the above headers....I1 is one output, just like I2 is the second output

[Altera_Forum]

So a little update....we got it to work, sort of. We ended up using different inputs for the IB's, so instead of having four of those switches that would generate the 8 outputs, we have 8 switches generating 8 outputs. Not exactly what we wanted, but o well. Now, I am trying to download it onto an Altera DE2, but I do not know how to do the clock pulses on the board. Any help? 

Thanks

[Altera_Forum]

--- Quote Start ---  So a little update....we got it to work, sort of. We ended up using different inputs for the IB's, so instead of having four of those switches that would generate the 8 outputs, we have 8 switches generating 8 outputs. Not exactly what we wanted, but o well. Now, I am trying to download it onto an Altera DE2, but I do not know how to do the clock pulses on the board. Any help? Thanks  --- Quote End ---   Hey Randallc To do the clock pulse for your board, you'll need the schematic from Altera or open one of their demo project and find what pin is assigned to the clock. For your project, if you know verilog or systemverilog , you can write it using case statements no problem