As I understand it, you have some inquries related to the trace length matching. For your information, generally for 40G Ethernet, there will be 10G x 4 bonded XCVR lanes. It is recommended for you to match the length for these lanes to ensure minimal lane-lane skew.
Just for ddditional information, you may also refer to the device datasheet ie "Transmitter Channel-to-channel Skew Specifications" in A10 device datasheet for max TX CH-CH skew within the FPGA.
Please let me know if there is any concern. Thank you.