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Hi,I used the PCIE HARD IP in the Cyclone IV GX starter kit, the Timequest showed that the setup SLACK is NEGATIVE(when the speed level of the device is C8).

WZhan10
Beginner
784 Views

It can be ok when I use the speed level C6.Do I have to use the C6 device if I want to use the PCIE IP ?PCIE.PNG

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1 Solution
SengKok_L_Intel
Moderator
93 Views

Hi John,

 

Please refer to table 9-1 below, some of the configuration is not suitable for C8 device.

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pci_express.pdf

 

Regards -SK LIm​

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4 Replies
SengKok_L_Intel
Moderator
93 Views

​Hi,

C8 speed grade is slower if compare with C6, and it seem like the core speed is not fast enough to process the PCIe data. For detail, need to use the timeQuest to understand the failure path and debug further.

Since the C6 speed grade is passing the timing, then it is obvious that your design need to run at faster speed grade, if this is the case, the I would suggest you to use C6.

 

Regards

-SK Lim (Intel) 

WZhan10
Beginner
93 Views

Hi,Lim

 

Thanks for your answer!

 

The chip on the Cyclone IV GX starter kit is Cyclone IV GX EP4CGX15BF14 FPGA, and it's C8 grade, this kit is used for developing PCIE.

I'm a little confused. why the C8 can not meet the timeQuest requirement of the PCIE IP.(I only use the PCIE IP now)

 

Has there ever been such a problem? How did other people deal with this problem? Do others use this FPGA in the application of PCIE.

 

I doubt if I have made a mistake..

 

Best regard

John

SengKok_L_Intel
Moderator
94 Views

Hi John,

 

Please refer to table 9-1 below, some of the configuration is not suitable for C8 device.

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pci_express.pdf

 

Regards -SK LIm​

View solution in original post

WZhan10
Beginner
93 Views

Hi Lim,

 

Thank you very much. You have solved my question.

I find it in the table 1-9 ^-^

 

Best Regards

John

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