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Hi, can anyone explain what test input vector does? im a total beginner in FPGA, im using De1- SoC for comparing partial tmr and tmr fault tolerance. first time posting here, so idk how to ask question in the forum, sorry in advance

AAzri1
Beginner
371 Views

module tiv (clk_50, reset, start, again, c22, c23, 

clk, i, pass, fail);

 

input clk_50, reset, start, again, c22, c23;

output clk, i, pass, fail;

reg clk = 1'b0;

reg [4:0]i;

reg s = 1'b0;

reg cond = 2'b00;

reg pass = 1'b0;

reg fail = 1'b0;

wire clk_out;

slowclock clock (clk_50, reset, clk_out);

always@(posedge clk_out) begin

clk = ~clk;

if (again) begin

clk = 1'b0;

s = 1'b0;

cond = 2'b00;

pass = 1'b0;

fail = 1'b0;

i = 5'b00000;

end

else begin

if (s) begin

case (cond)

2'b00: begin

i = 5'b00000;

if (c22 == 1'b0 && c23 == 1'b0) begin

cond = 2'b01;

i = i + 1;

end

else fail = 1'b1;

end

2'b01: begin

if (c22 == 1'b0 && c23 == 1'b0) begin

if (i == 5'b11111) pass = 1'b1;

else i = i + 1;

end

else fail = 1'b1;

end

endcase

end

else begin

if (start) s <= 1;

else s <= s;

end

end

end

endmodule

0 Kudos
1 Reply
AnandRaj_S_Intel
Employee
99 Views

Hi @AAzri1​ ,

 

Test input vector / stimulus are the inputs to your design/ DUT. Used to check the functional behavior of the design.

There are basically few testbench each have its own advantages and disadvantages.

  • Simple testbench
  • Self-checking testbench
  • Self-checking testbench with testvectors 

Work on above mentioned testbench.

 

Check below links

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_gs_msa_qii.pdf

https://www.youtube.com/watch?v=qZNL1C0TwY8

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Best Regards,

Anand

 

I have not checked your code

Reply