Hi,I would like to connect 16 adcs with LVDS interface to FPGA. Each ADC will use 600mbps data rate. I am looking for a development kit that is capable of handling this much data. Also I need at least 2gb ram for continuous data acquisition. I check datasheets of Arria 10 and V FPGAs they all have support 1.6Gbps data rate for LVDS. They have at least 120 LVDS pairs. Q: 1.6Gbps is total bandwidth or each individual LVDS can handle this much speed? I also checked development kits for Arria boards I couldn't find information about how many LVDS pairs are available for interfacing. Datasheets states that It has LVDS but for chip to chip communication between 2 FPGA pairs inside Board. Q: My question is which FPGA Dev. Kit of Altera suitable for interfacing this much (16) LVDS pairs and each of them will consume 600mbps data rate? Also board should have fast enough memory interface to collect data (2gb). I checked many of Altera's solutions and confused about it. I have experience with FPGA but never with this much requirements. Kind Regards,
A1: 1.6Gbps is bandwidth of each LVDS, but you need to carefully design your board to achieve that performanceA2: HSMC connector generally connect LVDS lines. "Arria V SoC Development Kit and SoC Embedded Design Suite" have 2GB of DDR3 memory but your requirements are incomplete..
My main purpose is making data acquisition system with FPGA through 16 LVDS connection with continuous 600Mbps data rate. (9.6Gbps total bandwidth)My requirements: Development board should have/handle 16 LVDS pairs with at least 600Mbps data rate. Max 2GB data will be collected with this much continuous data rate. I will process this data, create image and display it. So computer interface (PCI-e) can be a plus. I couldn't find how many LVDS pairs that inside HSMC connector in "Arria V SoC Development Kit and SoC Embedded Design Suite" dev. kit Kind Regards,