- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello
I'm gonna use "Cyclone V GX starter kit" + "Highspeed AD/DA Card" http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=73&no=278 I need to the "Highspeed AD/DA Card" schematic or How much the input & output impedance of the ADA card? best regards- Tags:
- Cyclone® V FPGAs
Link Copied
9 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
since I want to design an amplifier to amplify the out of ADA card plz help me!
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Hello I'm gonna use "Cyclone V GX starter kit" + "Highspeed AD/DA Card" http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=73&no=278 I need to the "Highspeed AD/DA Card" schematic or How much the input & output impedance of the ADA card? best regards --- Quote End --- Schematic is not present on documentation on board relative CD you can download from terasic site? Input output impedance is usually set to 50 Ohm as a standard for all high frequency application and or RF if not specified for a different value. Regards
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- since I want to design an amplifier to amplify the out of ADA card plz help me! --- Quote End --- Card provide a 2Vpp over 50Ohm so power can be calculated: 1Vpeak is equivalent to RMS sqrt of 2, power is square of voltage divided by impedance so 2/50 or 40mW . Converting 40mW to dBW get a result of -14dBW select an amplifier from the one meet the level you need. regards
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello
How much the minimal voltage sensitivity of the ADA card? logically it should be Vref/(2^14) but practically? Due to 2 ch 65MSPS ADC on the ADA card, How much time can I record two signals? I know most of Altera FPGA Boards have maximum 1GB RAM capacity... so what should I do if I want to record two signals for a few seconds? I really need your help and I want to handle my project with Altera Cyclone V+Terasic Tech ADA card Regards- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
record signals to do what? Still after long time you ask help without explain what is in your mind so we cannot open to see in it your goal... Record signals at what speed, what type of analysis is to be performed on and how fast they are and noise level too are unknown. about sensitivity again is impossible to answer before all parameter involved in a measure are on desk. Sorry to be so evasive at your eye but at my side I don't see too many details only you know. Regards- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Hi, record signals to do what? Still after long time you ask help without explain what is in your mind so we cannot open to see in it your goal... Record signals at what speed, what type of analysis is to be performed on and how fast they are and noise level too are unknown. about sensitivity again is impossible to answer before all parameter involved in a measure are on desk. Sorry to be so evasive at your eye but at my side I don't see too many details only you know. Regards --- Quote End --- I asked from Terasic Technical support they told me the minimum voltage sensitivity of the ADA board is Vref/(2^14) I want to sample two signals at the rate 30MHz or 50Mhz maximum and then apply Sliding FFT or Wavelet on them. but I know I should design a good interface for the ADA card. now my main problem is: I want to save sampled data on the SDRAM and then transfer them and FFT results to my laptop. How can I do it? I don't want to use Linux. How can I manage the SDRAM and USB and Ethernet connection? if I want to buy Cyclone V Starter board, can I do all? is there any prepared IP cores for managing SDRAM or USB for Nios soft processor? thanks
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi, 50MHz on two stream of 14 bit sound as 1.4 Gbps, so it is also difficult to sustained stream data to pc. not in some way compressed GigaLan has not enough bandwidth and also USB3 get saturated too.
If you accept sample some data then do FFT and Wavelet on chunk then you can transfer data to pc to do some postprocessing. So how long is sample to process from FFT, how many FFT point and how is wavelet applied to? RAW data has to be transferred to pc also? Cyclon V can manage this but the best is SOC with dual core ARM, if you wish to manage real time data processing forget Windows ( I HATE due is not real multitask nor SMP) and use task spreading from Linux platform or other embedded OS. ALso to do multiple transfer you need split process on thread and use one processor core, Nios can be used to manage task on low level as register programming and DMA coordination on FPGA fabric side. NOt sure this is the best but again too many details are missing. Regards Roberto- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Hi, 50MHz on two stream of 14 bit sound as 1.4 Gbps, so it is also difficult to sustained stream data to pc. not in some way compressed GigaLan has not enough bandwidth and also USB3 get saturated too. If you accept sample some data then do FFT and Wavelet on chunk then you can transfer data to pc to do some postprocessing. So how long is sample to process from FFT, how many FFT point and how is wavelet applied to? RAW data has to be transferred to pc also? Cyclon V can manage this but the best is SOC with dual core ARM, if you wish to manage real time data processing forget Windows ( I HATE due is not real multitask nor SMP) and use task spreading from Linux platform or other embedded OS. ALso to do multiple transfer you need split process on thread and use one processor core, Nios can be used to manage task on low level as register programming and DMA coordination on FPGA fabric side. NOt sure this is the best but again too many details are missing. Regards Roberto --- Quote End --- Only 1 sec RAW DATA is enough I don't want to work with Linux bcoz I'm not expert in Linux.. I think it takes long time to learn it some experts in Xilinx SOC have told me you can manage the RAM and USB with SOC easily without Linux. also told me SOC is better than Microblaze (is similar to Altera Nios) I'm a master student, All of my time is 7 month. DE-1 SOC board has only 512MB DDR3 RAM on the HPS and 64MB on the FPGA side Arria V GX Starter board has 256MB DDR3 RAM but has lots of resources. Cyclone V GX Starter board has 512MB LPDDR2 my main problem: which board is better?.. I need an "USB device port" or "Ethernet port" for transferring data to my laptop I know transferring the data over them needs IP core or writing some codes in FSM which one is better and easier? Nios or SOC (without Linux) ps: if I want to process on the FPGA I have to process 4096 point FFT or Continues Wavelet on the sampled data. Continues Wavelet needs Huge Convolution process. or I can transfer the RAW DATA to my laptop (2x50Mx2Byte=200Mbyte) and then apply the FFT or wavelet on them by Matlab.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Ok, I assume after 1 second sampling all stop there so data chunk is not so large and 64MB of ram are useful as buffer to store on main memory.
Final data is large 50Ms * 4 Byte -> about 200MB I don't see simple solution other than use Linux to manage data stream and also apply some software, 4096 point can be stored on fast FPGA memory as dual port, then changed to new sample by DMA, output buffer must be transferred away before restart a new FFT computation, this on Cyclon has no trouble and you can allocate multiple buffer then use main memory as storage. I don't see simple solution only using IP cores and Linux you state is difficult help a lot, program to transfer streaming to network or USB is not so complicated and can be debugged without touching hardware on FPGA fabric. I am using Linux on PC as main development and is faster on compilation, before Intel acquisition was more than 10 times faster, I am using Linux on SOC due I developed all network communication and software emulation on this platforn, I don't wish use windows is slow and cumbersome to have working software in it. Again you can simply allocate buffers then transfer by ftp or storage sharing or some other simple way ffrom Linux domain. If you don't have a support managing TCPIP or USB I suspect generate a big nightmare. You can find a lot of help on Linux, if your data can be transferred with some time try also evaluate interface Raspberry PI to FPGA and avoid use the complexity of DE1-SOC environment. De1-SOC has 1GB of ram not 512K organized as two devices 16x512 so you can feed both devices with the stream from both channel in parallel as 32 bit. http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=205&no=836&partno=2 Regards
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page