How are number of lanes in PCIe related to the actual data width I use in my application logic?

[SAnan1]

I am very confused about these things:

[a] Transfer rate

[b] Throughput

[c] line rate

[d] width of data transfer

[e] PCIE Express version

[f] number of lanes

[g] PCIE Express generations

Please break it down for me

[SengKok_L_Intel]

​Hi,

If you are using difference lanes number, e.g from x8 to x4, the bandwidth will be reduced, but the data width can be the same as the PCIe core clk can be reduced. In the PCIe HIP GUI, you should be able to see the option in the Hard IP mode.

Regards -SK

[SAnan1]

I have updated the question. Can you please break it down further. Please....with a very simple example.

[SengKok_L_Intel]

​Hi,

For transfer rate, line rate and throughput, you can get the answer from the following link Figure 1 & Table 1.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf

For some other basic PCIe specification, you can just refer to the Wikipedia:

https://en.wikipedia.org/wiki/PCI_Express

Regards -SK