I am very confused about these things:
[a] Transfer rate
[c] line rate
[d] width of data transfer
[e] PCIE Express version
[f] number of lanes
[g] PCIE Express generations
Please break it down for me
If you are using difference lanes number, e.g from x8 to x4, the bandwidth will be reduced, but the data width can be the same as the PCIe core clk can be reduced. In the PCIe HIP GUI, you should be able to see the option in the Hard IP mode.
For transfer rate, line rate and throughput, you can get the answer from the following link Figure 1 & Table 1.
For some other basic PCIe specification, you can just refer to the Wikipedia: