Quartus TimeQuest infers a PIN as a clock because I need to use it as the way of a clock for some reason. However, it's a not a clock and mostly used as a data in the design.
I couldn't find the "not a clock" assignment, so I tried the steps with a problem as below:
- Let's say the PIN name is signal, and I have two signals by using "assign signal_clk = signal;" and "assign signal_data = signal;";
- I'd like to use create_clock for signal_clk which is used as the way of a clock only, but I couldn't find the node when I tried to add a node of create_clock in TimeQuest.
- Note: There is no flip-flop but only wire between the PIN signal and signal_clk.
My questions are:
- Is there any way to let Quartus TimeQuest know it's not a clock?
- What's the reason that I couldn't find the node for signal_clk, may because there is no flip-flop that it's regarded as the PIN itself?
First of all, your description is very uncertain.
My answers to your questions are:
- There is no way in modern Quartus software to create "not a clock" assignment.
- To answer that you'd better attach RTL netlist.
Hope that helps.
Thank you for your information.
Sorry that I didn't describe it clearly.
For 1, thank you for letting me confirm there is no "not a clock" assignment any more.
For 2, the net signal_clk and signal_data couldn't be found as they were synthesized away. I could use synthesis attribute to avoid this which solved my issue.
Here are RTL code I mentioned above, which might be better to show as below:
input logic signal;
assign signal_clk = signal;
assign signal_data = signal;