Quartus TimeQuest infers a PIN as a clock because I need to use it as the way of a clock for some reason. However, it's a not a clock and mostly used as a data in the design.
I couldn't find the "not a clock" assignment, so I tried the steps with a problem as below:
My questions are:
First of all, your description is very uncertain.
My answers to your questions are:
Hope that helps.
Thank you for your information.
Sorry that I didn't describe it clearly.
For 1, thank you for letting me confirm there is no "not a clock" assignment any more.
For 2, the net signal_clk and signal_data couldn't be found as they were synthesized away. I could use synthesis attribute to avoid this which solved my issue.
Here are RTL code I mentioned above, which might be better to show as below:
input logic signal;
assign signal_clk = signal;
assign signal_data = signal;
Yes, it was solved by adding synthesis keep.
Then I could add clock constraint on "signal_clk" instead of "signal" as shown above.
Thank you for your help.
Sorry I didn't make the question clear, however, your information could help solving it.
It was solved by adding synthesis keep.