How can "Clock Controller application" Programs the clock generator on Arria 10 Dev board ?

[JET60200]

Hello,

We see there is a " Clock Controller Application" on Arria10 GX Dev Board's Development Kit folder. From Dev board user guide, we know it can be used to re-config   the clock generators on Arria 10 Dev board. But we don't know very clear how it can work from a Windows Application to communicate to FPGA on-board clock generator ?  Can you clarify a bit for details how it works to do that ?

Thanks a lot

[JET60200]

Another query : Does A10 FPGA need a dedicated specific fpga image to be running, to co-operate with "Windows Clock Controller application" , to re-config the on-board clock generator(i.e SI5338 ) ? If we develop our own FPGA sof image, and burn into A10 GX Dev Board, and this image doesn't contain I2C scheme. my understanding is that Windows "Clock Controller Applcation" will to not work any more, right ? Thanks a lot !!

[JET60200]

to be simple:  my question is : 

there're  "MAX CPLD" devices and "A10 GX FPGA" devices on A10 Dev Board, which device is used to implement I2C scheme to support windows "Clock Controller Application" to work together ? 

Best regards

[JET60200]

Hi @Angelica_S_Intel,  can you help on this , as expert  ?  Thanks  

[Deshi_Intel]

Hi,

There is no relationship between using "clock controller GUI" and "FPGA Quartus design".

• "clock controller GUI" is independent tool used to configure on board clock generator chip to provide user desired clock frequency input to FPGA. The status of FPGA is not important here

The guideline on using "clock controller GUI" is as below.

• Power up the dev kit board
• Launch the Quartus version that match with clock controller GUI version (refer to Quartus version suggested in dev kit website)
• Next launch clock controller GUI to modify clock frequency and save the setting. Then close clock controller GUI
• Finally, user can program/configure whatever FPGA image design into the FPGA

Thanks.

Regards,

dlim

[JET60200]

Hi @Deshi_Intel , 

""clock controller GUI" is independent tool used to configure on board clock generator chip to provide user desired clock frequency input to FPGA.  The status of FPGA is not important here"

How can PC tool "clock controller GUI" operate these hardware peripherals on-board ?  There must be some module wjich is on board to operate theese on-board i2c hardware,  right ?  what's this bridge module to config i2c peripheral hardware ?   CPLD ? 

[Deshi_Intel]

HI,

Your understanding is correct. We do have Max V CPLD on the Arria 10 GX dev kit board to manage board control operation.

Thanks.

Regards,

dlim

[JET60200]

Hi @Deshi_Intel ，

1)  Can you provide the full source project of " Max V CPLD on the Arria 10 GX dev kit board" ?

2)  Since we have a A10GX alike customer board,  if we want to develop a similar "Clock Control GUI Application" to control the on-board peripheral （i2c/）, can you provide  an example code of " Clock Controller GUI" ?  We want it as reference to evaluation how to develop it.  

Thanks in advance

[Deshi_Intel]

HI,

Sorry, MAX V FPGA board control design and clock controller GUI software is not part of product design that we sell to customer.

Therefore, I can't share the design source code with you.

Appreciate your understanding here.

Regards,

dlim