We see there is a " Clock Controller Application" on Arria10 GX Dev Board's Development Kit folder. From Dev board user guide, we know it can be used to re-config the clock generators on Arria 10 Dev board. But we don't know very clear how it can work from a Windows Application to communicate to FPGA on-board clock generator ? Can you clarify a bit for details how it works to do that ?
Thanks a lot
to be simple: my question is :
there're "MAX CPLD" devices and "A10 GX FPGA" devices on A10 Dev Board, which device is used to implement I2C scheme to support windows "Clock Controller Application" to work together ?
There is no relationship between using "clock controller GUI" and "FPGA Quartus design".
The guideline on using "clock controller GUI" is as below.
Hi @Deshi_Intel ,
""clock controller GUI" is independent tool used to configure on board clock generator chip to provide user desired clock frequency input to FPGA. The status of FPGA is not important here"
How can PC tool "clock controller GUI" operate these hardware peripherals on-board ? There must be some module wjich is on board to operate theese on-board i2c hardware, right ? what's this bridge module to config i2c peripheral hardware ? CPLD ?
Hi @Deshi_Intel ，
1) Can you provide the full source project of " Max V CPLD on the Arria 10 GX dev kit board" ?
2) Since we have a A10GX alike customer board, if we want to develop a similar "Clock Control GUI Application" to control the on-board peripheral （i2c/）, can you provide an example code of " Clock Controller GUI" ? We want it as reference to evaluation how to develop it.
Thanks in advance
Sorry, MAX V FPGA board control design and clock controller GUI software is not part of product design that we sell to customer.
Therefore, I can't share the design source code with you.
Appreciate your understanding here.