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How does memory mapping work in DE1-SoC between HPS-FPGA using FIFO?


After a few detail study on the data transfer between HPS and FPGA, I slowly have some idea on how it works.


I found a tutorial on data transfer between HPS and FPGA using memory mapped FIFO from rocketboards:


and also the project done by the lecturer from Cornell ece5760: https://people.ece.cornell.edu/land/courses/ece5760/DE1_SOC/HPS_peripherials/FPGA_addr_index.html, one thing that confuses me is that how they really write some data to the FIFO bridge address so that it can be received by the FPGA and perform some work on the FPGA side which described in verilog.

Take the example from Cornel ese5760, in the C file, I notice there is a line:


which responsible to write the data to the FIFO bridge. But on the top of the file I can't see any header he used to define that line:

#include <stdio.h> #include <string.h> #include <stdlib.h> #include <unistd.h> #include <fcntl.h> #include <sys/types.h> #include <sys/ipc.h> #include <sys/shm.h> #include <sys/mman.h> #include <sys/time.h> #include <math.h>     #define FPGA_ONCHIP_BASE 0xC8000000 #define FPGA_ONCHIP_SPAN 0x00001000   #define FIFO_BASE 0xC0000000 #define FIFO_SPAN 0x00001000   #define FIFO_WRITE (*(FIFO_write_ptr)) #define FIFO_READ (*(FIFO_read_ptr))     #define HW_REGS_BASE 0xff200000 #define HW_REGS_SPAN 0x00005000   #define WAIT {}   #define WRITE_FIFO_FILL_LEVEL (*FIFO_write_status_ptr) #define READ_FIFO_FILL_LEVEL (*FIFO_read_status_ptr) #define WRITE_FIFO_FULL ((*(FIFO_write_status_ptr+1))& 1 ) #define WRITE_FIFO_EMPTY ((*(FIFO_write_status_ptr+1))& 2 ) #define READ_FIFO_FULL ((*(FIFO_read_status_ptr+1)) & 1 ) #define READ_FIFO_EMPTY ((*(FIFO_read_status_ptr+1)) & 2 )   #define FIFO_WRITE_BLOCK(a) {while (WRITE_FIFO_FULL){WAIT};FIFO_WRITE=a;}   #define FIFO_WRITE_NOBLOCK(a,b) {b=!WRITE_FIFO_FULL; if(!WRITE_FIFO_FULL)FIFO_WRITE=a; }   #define FIFO_READ_BLOCK(a) {while (READ_FIFO_EMPTY){WAIT};a=FIFO_READ;}   #define FIFO_READ_NOBLOCK(a,b) {b=!READ_FIFO_EMPTY; if(!READ_FIFO_EMPTY)a=FIFO_READ;}

which will send the data to

hps_to_fpga_readdata ;

in the verilog file.


In the verilog code which instantiate the Qsys design:

.fifo_hps_to_fpga_out_readdata (hps_to_fpga_readdata),

 So what does the FIFO_WRITE_BLOCK means?


Another question, I found that there is a way to do memory mapping by generate a hps_0.h header file and include this file in C file, which is taught from the tutorial my_first_hps-fpga.

Comparing these 2 method, which one will provide faster data transfer speed?


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I am unsure on the Cornell tutorial, but is the line 36 which defines the FIFO_WRITE_BLOCK function the one you are looking for?


Looking at it, it seems that the function is the FIFO write's memory block.


For the data speed comparison, there is no performance specs that is documented that could be found, but based on my experience it highly depends on the users on which method is more convenience for them to execute.



yes, the line 36, I just saw that.

Does it means I just need to define that, and then straight away can use the FIFO_WRITE_BLOCK, regardless the headers...

Sorry my C is not quite well as I developed my function in Python, then only found that only C can do HPS-FPGA data transfer.

Thank you.




Based on the tutorial, yes as it was define in that coding, it can be used there. In the coding you may see the "send array to FIFO and read every time" section where this function gets called.


I found this similar tutorial that has some explanation, I am not really familiar with this tutorial but you may refer this link here for more info: